ATC25 데이터 시트보기 (PDF) - Atmel Corporation

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ATC25

Cell-based ASIC

Atmel Corporation 

ATC25 Summary

Compiled Asynchronous

RAM Megacells

The Atmel Asynchronous RAM compiler has bidirectional or separate I/O ports, and can

be configured in multi-bank form, with a maximum of four banks.

The range of permitted Asynchronous RAM megacell configurations is as follows:

Number of bits 128, .. 128K bits

Number of words 16, .. 4K

Word Size

8, .. 36 bits

The following table shows the range of performances for particular Asynchronous RAM

configurations under typical conditions.

Configuration

Density (Kbits/mm2)

Frequency (MHz)

Dynamic Power

(mW/MHz)

1K x 8 (8K bits)

40

380

0.24

2K x 16 (32K bits)

40

378

0.38

4K x 32 (128K bits)

50

293

0.63

Compiled Asynchronous

Dual-port RAM

Megacells

The Atmel Asynchronous Dual-port RAM has bidirectional or separate I/O ports, and

can be configured in multi-bank form, with a maximum of four banks.

The range of permitted Asynchronous Dual-port RAM Megacell configurations is as

follows:

Number of bits

128, .. 16K

Number of words(1) 64, .. 2K

Word Size(1)

2, .. 36 bits

Note: 1. Must be the same for both ports.

The following table shows the range of performances for particular Asynchronous Dual-

port RAM configurations under typical conditions.

Configuration

Density (Kbits/mm2)

Frequency (MHz)

Dynamic Power

(mW/MHz)

128 x 8 (1K bits)

22

305

0.09

256 x 16 (4K bits)

32

274

0.31

512 x 32 (16K bits)

36

248

0.41

9

1306DS–CBIC–09/02

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