CXB1582Q 데이터 시트보기 (PDF) - Sony Semiconductor

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CXB1582Q

Fibre Channel Receiver

Sony Semiconductor 

CXB1582Q

Pin

No.

Symbol

Type

Typical pin

I/O voltage

Equivalent circuit

VCCG

69 REFCLK

TTL

input

TTL level

REFCLK

VEET

Description

Reference clock

input.

This pin is used for

PLL frequency pull-in.

Input the clock with

1/20 frequency of the

serial data rate

during 1.0625Gbaud

mode or with 1/10

frequency of the

serial data rate

during 531.25Mbaud

VEET mode (around

53.125MHz in either

case).

External

part

70 RTCAP connec

—

-tion

pin

VCCG

VEEG

VCCT5

RTCAP

Connects the

capacitor which

determines the POR∗

(power-on reset

signal) low time.

(See Notes on

Operation and Fig. 4.)

VEET

71 POR∗

TTL

output

TTL level

VCCT5

VCCT3

POR∗

VEET

Power-on reset

signal output.

When the power is

turned on, POR∗

maintains low level

for approximately

100ns and then goes

to high level. (See

Notes on Operation

and Fig. 4.)

– 11 –

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