DS1202 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS1202 Datasheet PDF : 11 Pages
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DS1202, DS1202S
TIMING DIAGRAM: READ DATA TRANSFER Figure 5
RESET
CLOCK
DATA INPUT/
OUTPUT
tCC
tDC
0
tCDH
1
tCDD
7
COMMAND BYTE
tCDZ
TIMING DIAGRAM: WRITE DATA TRANSFER Figure 6
RESET
CLOCK
DATA INPUT/
OUTPUT
tCC
tDC
0
tR
tCL
tCDH
tCH
1
7
COMMAND BYTE
tCWH
tCCH
tF
NOTES:
1. All voltages are referenced to ground.
2. Logic one voltages are specified at a source current of 1 mA at VCC=5V and 0.4 mA at VCC=2V, VOH=VCC for
capacitive loads.
3. Logic zero voltages are specified at a sink current of 4 mA at VCC=5V and 1.5 mA at VCC=2V.
4. ICC1 is specified with I/O open, RST set to a logic 0, and clock halt flag=0 (oscillator enabled).
5. ICC is specified with the I/O pin open, RST high, SCLK=2 MHz at VCC=5V; SCLK=500 KHz, VCC=2V and clock
halt flag=0 (oscillator enabled).
6. RST, SCLK, and I/O all have 40KΩ pull–down resistors to ground.
7. Measured at VIH=2.0V or VIL=0.8V and 10 ms maximum rise and fall time.
8. Measured at VOH=2.4V or VOL=0.4V.
9. Load capacitance = 50 pF.
032697 8/11
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