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CXA3271GE 데이터 시트보기 (PDF) - Sony Semiconductor

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CXA3271GE
Sony
Sony Semiconductor Sony
CXA3271GE Datasheet PDF : 17 Pages
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CXA3271GE
Cs
Vcel
Cp
Sensor block
(192 × 128)
S4
Cf1
Sr
Vsl
S5
S3
Vdmy
Vsns
S_Amp
Cp'
S11 S2 S1
VM VH
VL
Sense amplifier block
(192)
S6
Cf2
Voi
Voo
Sc
S7
Ch1
O_Amp
VOS
Buf
Ch2
Output block
(1)
Aout
Fig. 2
• Fingerprint sensor operation (Fig. 2)
Description of characters
Cs: Capacitance formed between the finger and the metal electrode
Cp: Parasitic capacitance formed between the metal electrode and the silicon substrate
Cp': Capacitance for canceling Cp (Cp Cp')
Ch: Hold capacitance
Cf: Feedback capacitance for determining the gain
S: Switch
V: Node voltage
VH – VM VM – VL
• Detailed description of operation
(All switches are off in the default status.)
1. S1, S4, Sr and S11 are turned on, Vcel is set to voltage VH, and Vdmy is set to voltage VL.
Vcel accumulated charge (Cs + Cp) VH
Vdmy accumulated charge Cp' VL
2. S1, Sr and S11 are turned off.
3. S2 is turned on and Vsl is set to VM.
4. S4 is turned off.
5. Sr, S3 and S5 are turned on.
At this time, the charge level that moves from Vcel and Vdmy to Vsl (actually between capacitances) is:
(Cs + Cp) (VH – VM) – Cp' (VM – VL) Cs (VH – VM)
This means that the sense amplifier gain is determined independently of the parasitic capacitance,
making it possible to obtain the required large signal dynamic range.
Vsns = VM – Cs (VH – VM)/Cf1
The voltage Vsns determined as shown above is accumulated in Ch1.
6. S5 is turned off.
7. S6 is turned on and the Voi voltage is set to VOS.
8. S6 is turned off.
9. Sc and S7 are turned on.
At this time, the charge level that moves from Ch1 to Cf2 is:
(VOS – Vsns) Ch1
This determines the Voo voltage which is accumulated in Ch2 and output to Aout via the buffer.
– 10 –

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