CXA3271GE 데이터 시트보기 (PDF) - Sony Semiconductor
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CXA3271GE Datasheet PDF : 17 Pages
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CXA3271GE
Pin Description
Serial
No.
Land No.
Symbol
I/O
Description
2B SUB Power Substrate electrode (chip rear surface electrode) 3.3V.
1
2C AVDD Power Analog power supply 3.3V.
2
2D AVSS Power Analog GND.
3
2E TEST1 D/I Test mode selection. Connect to GND.
4
2F TEST2 D/I Test mode selection. Connect to GND.
5
3B MODE D/I Connect to GND.
6
3C DI0
D/I Gain setting input. (LSB)
7
3D DI1
D/I Gain setting input.
8
3E DI2
D/I Gain setting input. (MSB)
Sense start pulse input (negative pulse).
9
3F XSP
D/I The column and row shift registers and the timing generator are cleared
by this signal.
10
4B HD
D/I Connect to GND.
11
4C CLK
D/I Main clock. (1 to 2MHz)
12
4D
C_CLK D/I
Column shift register clock.
Connect to C_CK (4E).
13
4E
C_CK
D/O
Column shift register clock output.
Connect to C_CLK (4D).
14
4F ADCLK D/O Outputs the internally delayed input clock.
19
5B DVDD Power Digital power supply 3.3V.
18
5C DVSS Power Digital GND.
17
5D DVSS Power Digital GND.
16
5E CSRO D/O Column shift register final output. (Connection is not required.)
15
5F RSRO D/O Row shift register final output. (Connection is not required.)
24
6B VOS A/O Output amplifier reference voltage monitor. (1.65V)
23
6C VH
A/O
Sensor charge voltage monitor. (1 LSB = 80mV)
Adjustable within the range of 1.92 to 2.48V by the three bits DI[0:2].
22
6D VM
A/O Sense amplifier reference voltage monitor. (1.85V)
21
6E VL
A/O
Dummy cell charge voltage monitor for canceling parasitic capacitance.
VL = 2VM – VH
20
6F
VCS_S A/O
Sense amplifier current source bias monitor.
(Do not connect.)
7B SUB Power Substrate electrode (chip rear surface electrode) 3.3V.
28
7C AVDD Power Analog power supply 3.3V.
27
7D AVSS Power Analog GND.
26
7E AOUT A/O Sensor output.
25
7F
VCS_O A/O
Output amplifier and output buffer current source bias monitor.
(Do not connect.)
–4–
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