F25L004A-100PG 데이터 시트보기 (PDF) - [Elite Semiconductor Memory Technology Inc.

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F25L004A-100PG

3V Only 4 Mbit Serial Flash Memory

[Elite Semiconductor Memory Technology Inc. 

ESMT

F25L004A

64K-Byte Block-Erase

The 64K Byte Block-Erase instruction clears all bits in the

selected block to FFH. A Block-Erase instruction applied to a

protected memory area will be ignored. Prior to any Write

operation, the Write-Enable (WREN) instruction must be

executed. CE must remain active low for the duration of the any

command sequence. The Block-Erase instruction is initiated by

executing an 8-bit command, D8H, followed by address bits

[A23-A0]. Address bits [AMS-A16] (AMS = Most Significant address)

are used to determine the block address (BAX), remaining

address bits can be VIL or VIH. CE must be driven high before

the instruction is executed. The user may poll the Busy bit in the

software status register or wait TBE for the completion of the

internal self-timed Block-Erase cycle. See Figure 9 for the

Block-Erase sequence.

FIGURE 9 : 64-KBYTE BLOCK-ERASE SEQUENCE

Elite Semiconductor Memory Technology Inc.

Publication Date: Jan. 2009

Revision: 1.6

13/30

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