ESMT
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-
Enable-Latch bit to 1 allowing Write operations to occur.
The WREN instruction must be executed prior to any Write
(Program/Erase) operation. CE must be driven high before the
WREN instruction is executed.
CE
MODE3
SCK MODE0
0 12 3 45 67
SI
06
MSB
SO
HIGH IMPENANCE
FIGURE 13 : WRITE ENABLE (WREN) SEQUENCE
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-Enable-Latch
bit and AAI bit to 0 disabling any new Write operations from occurring.
CE must be driven high before the WRDI instruction is executed.
CE
MODE3
SCK MODE0
0 12 3 45 67
SI
SO
Figure 14 : WRITE DISABLE (WRDI) SEQUENCE
04
MSB
HIGH IMPENANCE
F25L004A
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009
Revision: 1.6
16/30