F25L32PA-86PAG 데이터 시트보기 (PDF) - [Elite Semiconductor Memory Technology Inc.

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F25L32PA-86PAG

3V Only 32 Mbit SerialFlash Memory with Dual

[Elite Semiconductor Memory Technology Inc. 

ESMT

INSTRUCTIONS

Instructions are used to Read, Write (Erase and Program), and

configure the device. The instruction bus cycles are 8 bits each

for commands (Op Code), data, and addresses. Prior to

executing any Page Program, Write Status Register, Sector

Erase, Block Erase, or Chip Erase instructions, the Write Enable

(WREN) instruction must be executed first. The complete list of

the instructions is provided in Table 5. All instructions are

synchronized off a high to low transition of CE . Inputs will be

accepted on the rising edge of SCK starting with the most

significant bit. CE must be driven low before an instruction is

F25L32PA

entered and must be driven high after the last bit of the instruction

has been shifted in (except for Read, Read ID, Read Status

Register, Read Electronic Signature instructions). Any low to high

transition on CE , before receiving the last bit of an instruction

bus cycle, will terminate the instruction in progress and return the

device to the standby mode.

Instruction commands (Op Code), addresses, and data are all

input from the most significant bit (MSB) first.

Table 5: Device Operation Instruction

Operation

Max.

Freq

1

SIN SOUT

Read

33 MHz 03H Hi-Z

Fast Read

Fast Read Dual Output12,13

Fast Read Dual I/O12, 14

Sector Erase4 (4K Byte)

Block Erase4, (64K Byte)

0BH Hi-Z

3BH

BBH

20H Hi-Z

D8H Hi-Z

Chip Erase

60H /

C7H

Hi-Z

2

SIN

SOUT

A23-A16 Hi-Z

A23-A16 Hi-Z

A23-A16

A23-A8

A23-A16 Hi-Z

A23-A16 Hi-Z

-

-

Bus Cycle 1~3

3

4

SIN SOUT SIN SOUT

A15-A8 Hi-Z A7-A0 Hi-Z

A15-A8 Hi-Z A7-A0 Hi-Z

A15-A8

A7-A0

A7-A0, M7-M0

DOUT0~1

A15-A8 Hi-Z A7-A0 Hi-Z

A15-A8 Hi-Z A7-A0 Hi-Z

-

-

-

-

Page Program (PP)

02H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z

Mode Bit Reset 15

50MHz FFH Hi-Z FFH Hi-Z

-

-

-

-

Deep Power Down (DP)

B9h Hi-Z -

-

-

-

-

-

Read Status Register

(RDSR) 6

05H Hi-Z

X

DOUT

(S7-S0)

-

-

-

-

Enable Write Status

Register (EWSR) 7

～ 50H Hi-Z -

-

-

-

-

-

Write Status Register

(WRSR) 7

Write Enable (WREN) 10

01H

Hi-Z

DIN

(S7-S0)

Hi-Z

DIN

(S15-S8)

Hi-Z

-.

-

06H Hi-Z -

-

-

-

-

-

Write Disable (WRDI)/ Exit

secured OTP mode

100MHz

04H

Hi-Z

-

-

-

-

-

-

Enter secured OTP mode

(ENSO)

B1H Hi-Z -

-

-

- -. -

Release from Deep Power

Down (RDP)

ABH Hi-Z -

-

-

-

-

-

Read Electronic Signature

(RES) 8

ABH Hi-Z X

X

X

XXX

RES in secured OTP mode

& not lock down

ABH Hi-Z X

X

X

XXX

RES in secured OTP mode

& lock down

ABH Hi-Z X

X

X

XXX

5

SIN SOUT

X DOUT0

XX

X

cont.

-

-

-

-

6

SIN SOUT

X DOUT1

X DOUT0

DOUT0~1

-

-

-

-

-

N

SIN SOUT

X cont.

X cont.

cont.

-

-

-

-

-

-

-

-

-

-

-

Up to

DIN0 Hi-Z DIN1 Hi-Z 256 Hi-Z

bytes

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X 15H -

-

-

-

X 35H -

-

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-

X 75H -

-

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-

Elite Semiconductor Memory Technology Inc.

Publication Date: Mar. 2009

Revision: 1.0

12/36

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