F25L32PA-86PAG 데이터 시트보기 (PDF) - [Elite Semiconductor Memory Technology Inc.

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F25L32PA-86PAG

3V Only 32 Mbit SerialFlash Memory with Dual

[Elite Semiconductor Memory Technology Inc. 

ESMT

F25L32PA

Fast Read Dual Output (50 MHz~100 MHz)

The Fast Read Dual Output (3BH) instruction is similar to the

standard Fast Read (0BH) instruction except the data is output

on bidirectional I/O pins (SIO0 and SIO1). This allows data to be

transferred from the device at twice the rate of standard SPI

devices. This instruction is for quickly downloading code from

Flash to RAM upon power-up or for applications that cache code-

segments to RAM for execution.

The Fast Read Dual Output instruction is initiated by executing

an 8-bit command, 3BH, followed by address bits [A23 -A0] and a

dummy byte. CE must remain active low for the duration of the

Fast Read Dual Output cycle. See Figure 4 for the Fast Read

Dual Output sequence.

CE

MODE3

SCK MODE0

0 12 34 56 78

15 16 23 24

31 32 39 40

43 44

47 48

51 52

55 56

Dummy

IO0 switches from In put to Ouput

SIO0

SIO1

MSB

3B

ADD.

ADD.

MSB

HIGH IMPENANCE

ADD.

6420 6420 6420 64206 4

DOUT

DOUT

DOU T

DOU T

D OUT

N

N+ 1

N+ 2

N+3

N+4

75317531 7531 753175

Note: The input data durin g the dummy clocks is “don’t care”.

However , the IO0 pin should be high-impefance piror to th e falling edge of the first data clock.

Figure 4: Fast Read Dual Output Sequence

Elite Semiconductor Memory Technology Inc.

Publication Date: Mar. 2009

Revision: 1.0

15/36

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