F25L32PA-100PAG 데이터 시트보기 (PDF) - [Elite Semiconductor Memory Technology Inc.
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F25L32PA-100PAG
[Elite Semiconductor Memory Technology Inc.
F25L32PA-100PAG Datasheet PDF : 36 Pages
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ESMT
F25L32PA
Fast Read Dual I/O (50 MHz~100 MHz)
The Fast Read Dual I/O (BBH) instruction is similar to the Fast
Read Dual Output (3BH) instruction, but with the capability to
input address bits [A23 -A0] two bits per clock.
To set mode bits [M7 -M0] after the address bits [A23 -A0] can
further reduce instruction overhead (See Figure 5). The upper
mode bits [M7 –M4] controls the length of next Fast Read Dual I/O
instruction with/without the first byte command code (BBH). The
lower mode bits [M3 –M0] are “don’t care”.
If [M7 –M0] = “AxH”, the next Fast Read Dual I/O instruction (after
CE is raised and the lowered) doesn’t need the command code
(See Figure 6). This way let the instruction sequence reduce 8
clocks and allows to enter address immediately after CE is
asserted low. If [M7 –M0] are the value other than “AxH”, the next
instruction need the first byte command code, thus returning to
normal operation. A Mode Bit Reset (FFH) also can be used to
reset mode bits [M7 –M0] before issuing normal instructions.
CE
MODE3
SCK MODE0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
27 28
31 32
35 36
39 40
IO0 switches from Input to Ouput
SIO0
SIO1
BB
MSB
HIG H IMPENANCE
22 20 18 16 14 12 10 8 6 4 2 0 6 4
6 42 0 6 4 2 0 6 4 2 0 6 4 20 6 4
23 21 19 17 15 13 11 9 7 5 3 1 7 5
A23- 16
A15-8
A7- 0
M7- 0
DOUT
DOU T
DOUT
DOUT
DOUT
N
N+1
N+2
N+ 3
N+ 4
753175317531 7531 75
Note: The mode bits [M3 -M0] are “d on’t care”.
However , the IO pins sh ould be high-impefance piror to the falling edge of the first data clock.
Figure 5: Fast Read Dual I/O Sequence ([M7 -M0] = 0xH or NOT AxH)
CE
MODE3
SCK MODE0
SIO0
SIO1
IO0 switches from In put to Ouput
22 20 18 16 14 12 10 8 6 4 2 0 6 4
6420 6420 6420 64206 4
23 21 19 17 15 13 11 9 7 5 3 1 7 5
A23- 16
A15- 8
A7-0
M7-0
DOUT
DOUT
DOU T
DOUT
D OUT
N
N+1
N+ 2
N+3
N+4
7531 7531 7531 753175
Note: The mode bits [M3 -M0] are “don’t care”.
However , the IO pins sh ould be high-impe fance piror to the fa ll ing edge of the fi rst data clock.
Figure 6: Fast Read Dual I/O Sequence ([M7 -M0] = AxH)
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 1.0
16/36
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