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LC662508A 데이터 시트보기 (PDF) - SANYO -> Panasonic

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LC662508A Datasheet PDF : 17 Pages
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LC662508A, 662512A, 662516A
Pin Function Overview
Pin
I/O
Overview
Output driver type
Options
P00
P01
P02
P03
I/O ports P00 to P03
Input or output in 4-bit or 1-bit units
I/O P00 to P03 support the halt mode
control function (This function can be
specified in bit units.)
Pch: Pull-up MOS type
Nch: Intermediate sink current
type
Pull-up MOS or
Nch OD output
Output level on
reset
P10
P11
P12
I/O
I/O ports P10 to P13
Input or output in 4-bit or 1-bit units
P13
Pch: Pull-up MOS type
Nch: Intermediate sink current
type
Pull-up MOS or
Nch OD output
Output level on
reset
P20/SI0
P21/SO0
P22/SCK0
P23/INT0
I/O ports P20 to P23
Input or output in 4-bit or 1-bit units
P20 is also used as the serial input SI0
pin.
P21 is also used as the serial output
I/O
SO0 pin.
P22 is also used as the serial clock
SCK0 pin.
P23 is also used as the INT0 interrupt
Pch: CMOS type
Nch: Intermediate sink current
type
Nch: +15V handling when OD
option selected
CMOS or Nch OD
output
request pin, and also as the timer 0
event counting and pulse width
measurement input.
State after a Standby mode
reset
operation
High or low
(option)
Hold mode:
Output off
Halt mode:
Output
retained
High or low
(option)
Hold mode:
Output off
Halt mode:
Output
retained
Hold mode:
Output off
H
Halt mode:
Output
retained
P30/INT1
P31/POUT0
P32/POUT1
I/O ports P30 to P32
Input or output in 3-bit or 1-bit units
P30 is also used as the INT1 interrupt
request.
I/O
P31 is also used for the square wave
output from timer 0.
P32 is also used for the square wave
and PWM output from timer 1.
P31 and P32 also support 3-state
outputs.
Pch: CMOS type
Nch: Intermediate sink current
type
Nch: +15V handling when OD
option selected
CMOS or Nch OD
output
Hold mode:
Output off
H
Halt mode:
Output
retained
P33/HOLD
Hold mode control input
Hold mode is set up by the HOLD
instruction when HOLD is low.
In hold mode, the CPU is restarted by
setting HOLD to the high level.
I
This pin can be used as input port P33
along with P30 to P32.
When the P33/HOLD pin is at the low
level, the CPU will not be reset by a
low level on the RES pin. Therefore,
applications must not set P33/HOLD
low when power is first applied.
P40/INV0I
P41/INV0O
P42/INV1I
P43/INV1O
I/O ports P40 to P43
I/O
Input or output in 4-bit or 1-bit units
Input or output in 8-bit units when used
in conjunction with P50 to P53.
Can be used for output of 8-bit ROM
data when used in conjunction with
P50 to P53.
Pch: Pull-up MOS type
CMOS type when the inverter
circuit option is selected
Nch: Intermediate sink current
type
Pull-up MOS or
Nch OD output
Output level on
reset
Inverter circuit
Dedicated inverter circuit (option)
High or low
or inverter
I/O (option)
Hold mode:
Port output
off, inverter
output off
Halt mode:
Port output
retained,
inverter
output
continues
Continued on next page.
No. 5997-5/17

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