PM7384-BI 데이터 시트보기 (PDF) - PMC-Sierra

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PM7384-BI

FRAME ENGINE AND DATALINK MANAGER 84P672

PMC-Sierra 

DATA SHEET

PMC-1990445

ISSUE 5

PM7384 FREEDM-84P672

FRAME ENGINE AND DATA LINK MANAGER 84P672

FIGURE 23 – DS3 DROP BUS FUNCTIONAL TIMING ..................................321

FIGURE 24 – DS3 ADD BUS ADJUSTMENT REQUEST FUNCTIONAL TIMING

..............................................................................................................322

FIGURE 25 – RECEIVE LINK TIMING............................................................323

FIGURE 26 – TRANSMIT LINK TIMING .........................................................323

FIGURE 27 – PCI READ CYCLE ....................................................................325

FIGURE 28 – PCI WRITE CYCLE ..................................................................326

FIGURE 29 – PCI TARGET DISCONNECT ....................................................327

FIGURE 30 – PCI TARGET ABORT................................................................328

FIGURE 31 – PCI BUS REQUEST CYCLE ....................................................328

FIGURE 32 – PCI INITIATOR ABORT TERMINATION ...................................329

FIGURE 33 – PCI EXCLUSIVE LOCK CYCLE ...............................................330

FIGURE 34 – PCI FAST BACK TO BACK.......................................................332

FIGURE 35 – SBI FRAME PULSE TIMING ....................................................337

FIGURE 36 – SBI DROP BUS TIMING ...........................................................338

FIGURE 37 – SBI ADD BUS TIMING ..............................................................339

FIGURE 38 – SBI ADD BUS COLLISION AVOIDANCE TIMING ....................339

FIGURE 39 – RECEIVE DATA TIMING...........................................................340

FIGURE 40 – TRANSMIT DATA TIMING ........................................................340

FIGURE 41 – PCI INTERFACE TIMING .........................................................342

FIGURE 42 – JTAG PORT INTERFACE TIMING............................................343

FIGURE 43 – 352 PIN ENHANCED BALL GRID ARRAY (SBGA) ..................345

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE vii

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