UAA3202 데이터 시트보기 (PDF) - Philips Electronics

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UAA3202

Frequency Shift Keying (FSK) receiver

Philips Electronics 

Philips Semiconductors

Frequency Shift Keying (FSK) receiver

Preliminary specification

UAA3202M

FSK demodulator

The limited IF signal is converted into baseband data by

means of a quadrature FM demodulator consisting of an

all-pass filter and a mixer stage. No alignment of the

demodulator is necessary. The demodulator centre

frequency is set by a capacitor external to the device.

The demodulator provides a large audio bandwidth in

order to allow high data rate applications.

The demodulator can detect a small IF frequency deviation

even if a relatively large IF frequency offset is

encountered.

Data filters

After demodulation a two-stage data filtering circuit is

provided in order to suppress unwanted frequency

components. Two R/C low-pass filters with on-chip

resistors are provided which are separated by a buffer

stage.

Data slicer

Data detection is provided by means of a level comparator

with adaptive slice reference. After the first data filter stage

the pre-filtered data is split into two parts. One part passes

the second data filter stage and is fed to the positive

comparator input.

The other path is fed to an integration circuit with a large

time constant in order to derive the average value

(DC component) as an adaptive slice reference which is

presented to the negative comparator input. The adaptive

reference enables the received data over a large range of

demodulator frequency offsets to be detected.

The integration circuit consists of a simple R/C low-pass

filter with on-chip resistor. The level comparator output is

designed as an open-collector with internal pull-up.

Power-down circuitry

The device provides a power-down mode. While in

power-down mode the device disables the majority of the

internal circuits and consumes extremely low current.

Measures are taken to allow fast receiver settling when

normal operation is resumed. Thus circuits with large time

constants are only powered down partly or provide a high

impedance during power-down in order to avoid the

discharge of external capacitors as much as possible.

Power-down mode is entered when the control input is

active HIGH. The control input provides an internal pull-up

resistor of high impedance.

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL

VCC

Tamb

Tstg

Vesd

PARAMETER

supply voltage

operating ambient temperature

storage temperature

electrostatic handling

pins 4 and 5

pins 18 and 19

all other pins

CONDITIONS

note 1

MIN.

−0.3

−40

−55

−2 000

−1 500

−2 000

MAX.

+8.0

+85

+125

+1 500

+2 000

+2 000

Note

1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor.

UNIT

V

°C

°C

V

V

V

THERMAL CHARACTERISTICS

SYMBOL

PARAMETER

Rth j-a

thermal resistance from junction to ambient in free air

VALUE

125

UNIT

K/W

1997 Aug 12

6

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