HM6P5331 데이터 시트보기 (PDF) - Hynix Semiconductor
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HM6P5331 Datasheet PDF : 10 Pages
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Pin Assignment
PRELIMINARY
Pin Description
Leadless Grid Array Package
Thin Shrink Small Outline Package ™
Pin No.
HM6C5332
24-pin LGA
Package
24
2
3
4
5
6
7
8
10
11
12
14
15
Pin No.
HM6C5332
20-pin TSSOP
Package
PIN
NAME
1
VDDRF
2
VPPRF
3
DoRF
4
VSRFD
5
finRF
6
VIRF
7
VSRFA
8
OSCin
9
VSS
10
FoLD
11
Clock
12
Data
13
LE
I/O
Description
Power supply voltage input for RF analog and RF digital circuits. Input may
range from 2.7V to 3.6V. VDDRF must equal VDDIF. Bypass capacitors
-
should be placed as close as possible to this pin and be connected directly
to the ground plane.
- Power Supply for RF charge pump. Must be ≥ VDDRF.
Internal RF charge pump output. For connection to a loop filter for driving
O
the input of an external VCO.
- Ground for RF digital circuitry.
I RF prescaler input. Small signal input from the VCO.
This pin is to provide a bypass capacitor to the internal voltage supply and
- bypass capacitor must be placed between this pin and RF analog GND(Pin
7). With a slight performance degradation, this pin may be NC.
- Ground for RF analog circuitry.
Oscillator input. The input has a VDDRF/2 input threshold and can be
I
driven from an external CMOS or TTL logic gate.
- Ground for data interface, FoLD, and oscillator circuits.
Multiplexed output of the RF/IF programmable or reference dividers, and
O
RF/IF lock detect signals. CMOS output(See Programmable Modes)
High impedance CMOS Clock input. Data for the various counters is
I
clocked in on the rising edge, into the 22-bit shift register.
Binary serial data input. Data entered MSB first. The last two bits are the
I
control bits. High impedance CMOS input.
Load enable high impedance CMOS input. When LE goes HIGH, data
I stored in the shift register is loaded into one of the 4 appropriate
latches(control bit dependent).
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