HMS81016E 데이터 시트보기 (PDF) - Hynix Semiconductor

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HMS81016E

8-BIT SINGLE-CHIP MICROCONTROLLERS

Hynix Semiconductor 

HMS81004E/08E/16E/24E/32E

14.1 Interrupt priority and sources

Each interrupt vector is independent and has its own pri-

ority. Software interrupt (BRK) is also available. Interrupt

14.2 Interrupt control register

I flag of PSW is a interrupt mask enable flag. When I flag

= “0”, all interrupts become disable. When I flag = “1”, in-

terrupts can be selectively enabled and disabled by con-

tents of corresponding Interrupt Enable Register. When

interrupt is occured, interrupt request flag is set, and Inter-

rupt request is detected at the edge of interrupt signal. The

accepted interrupt request flag is automatically cleared

during interrupt cycle process. The interrupt request flag

maintains “1” until the interrupt is accepted or is cleared in

program. In reset state, interrupt request flag register

(IRQH, IRQL) is cleared to “0”. It is possible to read the

state of interrupt register and to mainpulate the contents of

register and to generate interrupt. (Refer to software inter-

rupt)

source classification is shown in Table 14-1.

Reset/Interrupt

Hardware Reset

Key Scan

External Interrupt1

External Interrupt2

Timer0

Timer1

Timer2

Watch Dog Timer

Basic Interval Timer

BRK Instruction

Symbol

RESET

KSCNR

INT1R

INT2R

T0R

T1R

T2R

WDTR

BITR

BRK

Table 14-1 Interrupt Source

Priority

-

1

2

3

4

5

6

7

8

-

48

JUNE 2001 Ver 1.00

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