HMS87C4260 데이터 시트보기 (PDF) - Hynix Semiconductor
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HMS87C4260 Datasheet PDF : 110 Pages
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HMS81C4x60
NO.
MNENONIC
5 LDYA dp
6 STYA dp
7 SUBW dp
OP
CODE
7D
DD
3D
4. Bit Manipulation
BYTE
NO.
2
2
2
CYCLE
NO
5
5
5
OPERATION
Load YA : YA ← (dp+1)(dp)
Store YA : (dp+1)(dp) ← YA
16-bits substract without carry : YA ← YA - (dp+1)(dp)
NO.
MNENONIC
1 AND1 M.bit
2 AND1B M.bit
3 BIT dp
4 BIT !abs
5 CLR1 dp.bit
6 CLR1A A.bit
7 CLRC
8 CLRG
9 CLRV
10 EOR1 M.bit
11 EOR1B M.bit
12 LDC M.bit
13 LDCB M.bit
14 NOT1 M.bit
15 OR1 M.bit
16 OR1B M.bit
17 SET1 dp.bit
18 SETA1 A.bit
19 SETC
20 SETG
21 STC M.bit
22 TCLR1 !abs
23 TSET1 !abs
OP
CODE
8B
8B
0C
1C
y1
2B
20
40
80
AB
AB
CB
CB
4B
6B
6B
x1
0B
A0
C0
EB
5C
3C
BYTE
NO.
3
3
2
3
2
2
1
1
1
3
3
3
3
3
3
3
2
2
1
1
3
3
3
CYCLE
NO
4
4
4
5
4
2
2
2
2
5
5
4
4
5
5
5
4
2
2
2
6
6
6
OPERATION
Bit AND C-flag : C ← C ^ (M.bit)
Bit AND C-flag and NOT : C ← C ^ ~(M.bit)
Bit test A with memory :
Z ← A ^ M, N ← (M7), V ← (M6)
Clear bit : (M.bit) ← “0”
Clear A.bit : (A.bit) ← “0”
Clear C-flag : C ← “0”
Clear G-flag : G ← “0”
Clear V-flag : V ← “0”
Bit exclusive-OR C-flag : C ← C ⊕ (M.bit)
Bit exclusive-OR C-flag and NOT : C ← C ⊕ ∼(M.bit)
Load C-flag : C ← (M.bit)
Load C-flag with NOT : C ← ~(M.bit)
Bit complement : (M.bit) ← ~(M.bit)
Bit OR C-flag : C ← C V (M.bit)
Bit OR C-flag and NOT : C ← C V ~(M.bit)
Set bit : (M.bit) ← “1”
Set A.bit : (A.bit) ← “1”
Set C-flag : C ← “1”
Set G-flag : G ← “1”
Store C-flag : (M.bit) ← C
Test and clear bits with A :
A - (M), (M) ← (M) ^ ~(A)
Test and set bits with A :
A - (M), (M) ← (M) V (A)
5. Branch / Jump Operation
NO.
MNENONIC
1 BBC A.bit,rel
2 BBC dp.bit,rel
3 BBS A.bit,rel
4 BBS dp.bit,rel
5 BCC rel
6 BCS rel
7 BEQ rel
8 BMI rel
9 BNE rel
10 BPL rel
11 BRA rel
12 BVC rel
13 BVS rel
OP
CODE
y2
y3
x2
x3
50
D0
F0
90
70
10
2F
30
B0
BYTE
NO.
2
3
2
3
2
2
2
2
2
2
2
2
2
CYCLE
NO
4/6
5/7
4/6
5/7
2/4
2/4
2/4
2/4
2/4
2/4
4
2/4
2/4
OPERATION
Branch if bit clear :
if(bit) = 0, then PC ← PC + rel
Branch if bit clear :
if(bit) = 1, then PC ← PC + rel
Branch if carry bit clear :
if(C) = 0, then PC ← PC + rel
Branch if carry bit set : If (C) =1, then PC ← PC + rel
Branch if equal : if (Z) = 1, then PC ← PC + rel
Branch if munus : if (N) = 1, then PC ← PC + rel
Branch if not equal : if (Z) = 0, then PC ← PC + rel
Branch if not minus : if (N) = 0, then PC ← PC + rel
Branch always : PC ← PC + rel
Branch if overflow bit clear :
If (V) = 0, then PC ← PC + rel
Branch if overflow bit set :
If (V) = 1, then PC ← PC + rel
FLAG
NVGBHIZC
N-----Z-
--------
NV - - H - ZC
FLAG
NVGBHIZC
-------C
-------C
MM - - - - Z -
--------
--------
-------0
--0-----
-0--0---
-------C
-------C
-------C
-------C
--------
-------C
-------C
--------
--------
-------1
--1-----
--------
N-----Z-
N-----Z-
FLAG
NVGBHIZC
--------
--------
MM - - - - Z -
--------
--------
--------
--------
--------
--------
--------
--------
November 2001 Ver 1.1
107
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