A3951 데이터 시트보기 (PDF) - Allegro MicroSystems
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A3951 Datasheet PDF : 12 Pages
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3951
FULL-BRIDGE
PWM MOTOR DRIVER
FUNCTIONAL BLOCK DIAGRAM
PHASE
ENABLE
UVLO
& TSD
REF/ BRAKE
9R
1.5 V
BLANKING
VCC
R
Q
S
PWM LATCH
+–
SENSE
RS
RC
R
GROUND
VTH
10
SUFFIX 'W',
R θJT = 2.0°C/W
8
SUFFIX 'B',
RθJT = 6.0°C/W
6
Dwg. FP-036-1
TRUTH TABLE
4
SUFFIX 'W', R θJA = 38°C/W
2
SUFFIX 'B', R θJA = 43°C/W
0
25
50
75
100
TEMPERATURE IN °C
125
150
Dwg. GP-032A
BRAKE ENABLE PHASE
H
H
X
OUTA
Z
OUTB
Z
DESCRIPTION
Outputs Disabled
H
L
H
H
L
Forward
H
L
L
L
H
Reverse
L
X
X
L
L
Brake, See Note
X = Irrelevant Z = High Impedance (source and sink both off)
NOTE: Includes internal default Vsense level for over-current protection.
115 Northeast Cutoff, Box 15036
2
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1994, 2000 Allegro MicroSystems, Inc.
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