ICS1522M 데이터 시트보기 (PDF) - Integrated Circuit Systems
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ICS1522M
Integrated Circuit Systems
ICS1522M Datasheet PDF : 13 Pages
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ICS1522
Power-On Initialization
The ICS1522 has an internal power-on reset circuit that
sets the frequency of the CLK+and CLK- outputs to be half
the crystal or reference frequency assuming that they are
between 10 MHz and 25 MHz (refer to default settings in
Register Definition). Because the power-on reset circuit is
on the VDD supply, and because that supply is filtered,
care must be taken to allow the reset to de-assert before
programming. A safe guideline is to allow 20 microseconds
after the VDD supply reaches four volts.
Board Test Support
It is often desirable to statically control the levels of the
output pins for circuit board test. The ICS1522 supports
this through a register programmable mode, AUXEN. When
this mode is set, AUXCLK will directly control the logic
levels of the CLK+ and CLK- pins while OMUX1, OMUX2,
OMUX3, and OMUX4 will control OUT1, OUT2, OUT3
and OUT4, respectively.
Power Supplies and Decoupling
The ICS1522 has three VSS pins to reduce the effects of
package inductance. Both pins are connected to the same
potential on the die (the ground bus). These pins should
connect to the ground plane of the video board as close to
the package as is possible.
The ICS1522 has a VDDO pin which is the supply of +5
volt power to all output drivers. This pin should be connected
to the power plane (or bus) using standard high-frequency
decoupling practice. That is, capacitors should have low
series inductance and be mounted close to the ICS1522.
The VDD pin is the power supply pin for the PLL synthesizer
circuitry and other lower current digital functions. We
recommend that RC decoupling or zener regulation be
provided for this pin (as shown in the recommended
application circuitry). This will allow the PLL to “track”
through power supply fluctuations without visible effects.
Pin Discriptions
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PIN NAME
IPUMP
SDATA
SCLK
SELn
AVDD
XTAL1/EXTREF
XTAL2
FINE
VSS
VSS
OUT4
OUT3
VDDO
OUT2
OUT1
VSS
IPRG
CLK-
CLK+
VDD
PDEN
EXTFBK
EXTVCO
VVCO
TYPE
OUT
IN/OUT
IN
IN
PWR
IN
OUT
IN
PWR
PWR
OUT
OUT
PWR
OUT
OUT
PWR
IN
OUT
OUT
PWR
IN
IN
IN
IN
DESCRIPTION
Charge Pump output (External loop filter applications)
Serial Data Input/Output
Serial Clock Input
Serial Port enable (active Low)
Analog +5 Volt Supply
External Reference Input / Xtal Oscillator Input
Xtal Oscillator Output
Fine Phase Adjust Input
Ground
Ground
Output 4
Output 3
Output Driver +5 Volt Supply
Output 2
Output 1
Ground
Output Driver Current Programming Input
Differential CLK - Output
Differential CLK + Output
Digital +5 Volt Supply
Phase Detector Enable (Active High)
External Feedback Input
External VCO input
VCO Control Voltage Input (External loop filter applications)
4
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