ICS1522M 데이터 시트보기 (PDF) - Integrated Circuit Systems

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ICS1522M

User-ProgrammableVideo Clock Generator/ Line-Locked Clock Regenerator

Integrated Circuit Systems 

Serial ProgrammingTiming Diagram

ICS1522

NOTES:

1. R/Wn, READ=1 and WRITE=0

2. Address and data transmitted least significant bit first

3. 16 Positive-edge clocks required for complete data read/write (1-R/Wn, 3-Address,

11-Data, and 1 load data W/SELn HIGH)

4. SELn’s positive and negative transitions must occur on the same state of SCLK

5. An ICS1522 read consists of two consecutive cycles (1st cycle - SDATA is an input,

2nd cycle - SDATA is an output)

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