AV1886M 데이터 시트보기 (PDF) - Integrated Circuit Systems

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AV1886M

FDDI / Fast Ethernet PHYceiver™

Integrated Circuit Systems 

ICS1886

The current ICS1886 device provides a single

TTL-compatible input, carrier detect (CD~).

When carrier detect is asserted, the ICS1886

locks to the incoming receive data. When

carrier detect is deasserted, or if carrier detect

is asserted and no data is present on the receive

inputs, the PLL will free run and continue to

provide RXCLK at the nominal 25 MHz

frequency. This provides a continuous Receive

clock source, even if CD~ is always tied to

ground.

If a true signal detect is required by a chip that

connects to the ICS1886, a simple, low cost

PECL to CMOS converter can be used. The

following circuits implement this function:

These circuits provide PECL to CMOS

conversion for less than $0.80 in single unit

quantities. Note that the LM393 has two

amplifiers, so the unused one is tied inactive.

A running production change will be made to

the ICS1886 to change the CD~ input to PECL.

Therefore, boards should be layed out with a

direct normal PECL termination connection

stuffing option. This allows either version of

the part to be used by stuffing one of two sets

of external components. A version of this

circuit is shown in the diagram above.

CD PECL Input: Board Layout Options

Option 1

Differential PECL to CMOS Conversion Circuit

Option 2

Single-Ended PECL to CMOS Conversion Circuit

8

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