ISP1181 데이터 시트보기 (PDF) - Philips Electronics

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ISP1181

Full-speed Universal Serial Bus interface device

Philips Electronics 

Philips Semiconductors

ISP1181

Full-speed USB interface

Table 2: Pin description for TSSOP48

Symbol [1]

Pin Type Description

DATA13

21 I/O bit 13 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

DATA12

22 I/O bit 12 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

DATA11

23 I/O bit 11 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

DATA10

24 I/O bit 10 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

GND

25 -

ground supply

Vref(5.0)

DATA9

26 -

I/O pin reference voltage (3.0 to 5.5 V)

27 I/O bit 9 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

DATA8

28 I/O bit 8 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

DATA7

29 I/O bit 7 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

DATA6

30 I/O bit 6 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

DATA5

31 I/O bit 5 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

DATA4

32 I/O bit 4 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

DATA3

33 I/O bit 3 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

DATA2

34 I/O bit 2 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

DATA1

35 I/O bit 1 of D[15:0]; bi-directional data line (slew-rate controlled

output, 4 mA)

GND

36 -

ground supply

VCC(3.3)

37 -

supply voltage (3.0 to 3.6 V); leave this pin unconnected

when using the internal regulator

AD

38 I/O multiplexed bi-directional address and data line; represents

address A0 or bit 0 of D[15:0] in conjunction with input ALE;

level-sensitive input or slew-rate controlled output (4 mA)

Address phase: a HIGH-to-LOW transition on input ALE

latches the level on this pin as address A0 (1 = command,

0 = data)

Data phase: during reading this pin outputs bit D[0]; during

writing the level on this pin is latched as bit D[0]

A0

39 I

address input; selects command (A0 = 1) or data (A0 = 0); in

a multiplexed address/data bus configuration this pin is not

used and must be tied HIGH (connect to VCC or Vreg(3.3))

RD

40 I

read strobe input

WR

41 I

write strobe input

9397 750 06896

Objective specification

Rev. 01 — 13 March 2000

© Philips Electronics N.V. 2000. All rights reserved.

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