ISP1181 데이터 시트보기 (PDF) - Philips Electronics
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ISP1181 Datasheet PDF : 69 Pages
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Philips Semiconductors
ISP1181
Full-speed USB interface
7.7 Voltage regulator
A 5 V to 3.3 V voltage regulator is integrated on-chip to supply the analog transceiver
and internal logic. This voltage is available at pin Vreg(3.3) to supply an external 1.5 kΩ
pull-up resistor on the D+ line. Alternatively, the ISP1181 provides SoftConnect
technology via an integrated 1.5 kΩ pull-up resistor (see Section 7.4).
7.8 PLL clock multiplier
A 6 MHz to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip.
This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No
external components are required for the operation of the PLL.
7.9 Parallel I/O (PIO) and Direct Memory Access (DMA) interface
A generic PIO interface is defined for speed and ease-of-use. It also allows direct
interfacing to most microcontrollers. To a microcontroller, the ISP1181 appears as a
memory device with an 8/16-bit data bus and an 1-bit address bus. The ISP1181
supports both multiplexed and non-multiplexed address and data buses.
The ISP1181 can also be configured as a DMA slave device to allow more efficient
data transfer. One of the 14 endpoint FIFOs may directly transfer data to/from the
local shared memory. The DMA interface can be configured independently from the
PIO interface.
8. Modes of operation
The ISP1181 has four bus configuration modes, selected via pins BUS_CONF1 and
BUSCONF0:
Mode 0
Mode 1
Mode 2
Mode 3
16-bit I/O port shared with 8-bit or 16-bit DMA port
separate 8-bit I/O port and 8-bit DMA port
8-bit I/O port shared with 8-bit or 16-bit DMA port
reserved.
The bus configurations for each of these modes are given in Table 3. Typical interface
circuits for each mode are given in Section 20.1.
Table 3: Bus configuration modes
Mode
BUS_CONF[1:0] PIO width
0
0
0 D[15:0]
1
0
1 D[7:0]
2
1
0 D[7:0]
3
1
1 reserved
DMA width
DMAWD = 0 DMAWD = 1
D[7:0];
D[15:0]
D[15:8]
illegal
D[7:0]
D[15:0]
reserved
reserved
Description
multiplexed address/data on pin AD0;
bus is shared by 16-bit I/O port and 8-bit
or 16-bit DMA port
multiplexed address/data on pin AD0;
bus has separate I/O port (8-bit) and
DMA port (8-bit)
multiplexed address/data on pin AD0;
bus is shared by 8-bit I/O port and 8-bit
or 16-bit DMA port
reserved
9397 750 06896
Objective specification
Rev. 01 — 13 March 2000
© Philips Electronics N.V. 2000. All rights reserved.
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