STLC5048 데이터 시트보기 (PDF) - STMicroelectronics

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STLC5048

FULLY PROGRAMMABLE FOUR CHANNEL CODEC AND FILTER

STMicroelectronics 

STLC5048

quency is automatically detected by the device the first time both MCLK and FS are applied and becomes active

after the second FS period. MCLK synchronises both the transmit data (DXA/B) and the receive data (DRA/B).

The Frame Sync. signal FS is the common time base for all the four channels.

Transmit and Receive programmable Time-Slots are framed by an internal sync. signal that can be coincident

with FS or delayed of 1 or 7 MCLK cycles depending on the programming of PCMSH register.

Two PCM ports are available: every channel can be connected to a different PCM port by means of PCMCOM

register.

DXA/B represents the transmit PCM interface. It remains in high impedance state except during the assigned

time slots during which the PCM data byte is shifted out on the rising/falling edge of MCLK according to the TE

bit of PCMCOM register. The four channels can be shifted out in any possible timeslot as defined by the DXTS

registers. The assigned Time Slot (Transmit and Receive) takes place in the 8 MCLK cycles following the rising

edge of FS.

The data can be shifted out on port A and/or B according to PCMCOM register.

If one CODEC is set in Power Down by software programming the corresponding time slot is set in High Imped-

ance. When linear coding mode is selected by CONF register programming the output channel will need two

consecutive time slots (see register description).

DRA/B represents the receive PCM interface. It remains inactive except during the assigned time slots during

which the PCM data byte is shifted in on the falling edge of MCLK. The four channels are shifted in any possible

time slot as defined by the DRTS registers.

If one Codec is set in Power Down by software programming the corresponding time slot is not loaded and the

VFRO output is kept at steady AGND level.

INSTRUCTION BYTE STRUCTURE

First Byte (Address or command ID)

Following Bytes (Data)

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

R/W I6 I5 I4 I3 I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 D0

R/W=0: Write Operation

R/W=1: Read Operation

I6..I0: Instruction Identifier: it can be a register address or a command identifier.

The number of data bytes depends on the instruction type. The first bit of a byte is the MSB, the first byte of an instruction is the LSByte.

When linear coding mode is selected by CONF register programming the input channel will need two consecu-

tive time slots (see register description).

The data can be shifted in from port A or B according to the PCMCOM register.

TSXA/B represents the Transmit Time Slot (open drain output, 3.2mA). Normally it is floating in high impedance

state except when a time slot is active on the DXA/B output. In this case TSXA/B output pulls low to enable the

backplane line driver. Should be strapped to VSS when not used.

Finally by means of the LOOPB register it is possible to implement a digital or analog loopback on any of the

selected channels.

MCU CONTROL INTERFACE

The MCU serial control interface consists of 4 pins.

CCLK: Control Clock

CI: Serial Data In

CO: Serial Data Out

CS: Chip Select Input

Control instructions require at least two bytes: however two single byte instructions are also provided.

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