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LS7266R1

24-BIT DUAL-AXIS QUADRATURE COUNTER

LSI Corporation  

Flag Register: XFLAG and YFLAG

The FLAG registers hold the status information of the CNTRs and can be read out on the data bus. The E bit of a

FLAG register is set to 1 when the noise pulses at the quadrature inputs are wide enough to be validated by the

input filter circuits. E = 1 indicates excessive noise at the inputs but not a definite count error. Once set, E can

only be reset via the RLD.

FLAG

7 6 5 4 32 1 0

BT: Borrow Toggle flip-flop.

Toggles every time CNTR underflows.

CT: Carry toggle flip-flop.

Toggles every time CNTR overflows.

CPT: Compare toggle flip-flop.

Toggles every time PR equals CNTR.

S: Sign flag. Set to1 when CNTR underflows.

Reset to 0 when CNTR overflows.

E: Error flag. Set to 1 when excessive noise is present at the count

inputs in quadrature mode. Irrelevant in non-quadrature mode.

U/D: Up/Down flag. Set to 1 when counting up

and reset to 0 when counting down.

IDX: Index. Set to 1 when selected index input is at active level.

0 : Not used. Always reset to 0.

Filter Clock Prescalers: XPSC and YPSC

Each PSC is an 8-bit programmable modulo-N down counter, driven by the FCK clock. The factor N is down loaded

into a PSC from the associated PR low byte register PR0. The PSCs provide the ability to generate independent filter

clock frequencies for each channel. The PSCs generate the internal filter clock, FCKn used to

validate inputs XA, XB, YA, YB in the quadrature mode.

Final filter clock frequency fFCKn = ( fFCK/(n+1) ) , where n = PSC = 0 to FFH. For proper counting in the quadrature

mode, fFCKn ≥ 8fQA (or 8fQB), where fQA and fQB are the clock frequencies at inputs A and B. In non-quadrature mode

filter clock is not needed and the FCK input (Pin 2), should be tied to VDD.

Reset and Load Signal Decoders: XRLD and YRLD

Following functions can be performed by writing a control byte into an RLD: Transfer PR to CNTR, Transfer

CNTR to OL, reset CNTR, reset FLAG and reset BP.

RLD

7 6 5 4 3 21 0

0: NOP

1: Reset BP

0

: NOP

0

1

0 : Reset CNTR

0 : Reset BT, CT, CPT,S

1

1

: Reset E

1

0

: NOP

0

1 : Transfer PR to CNTR

0

(Note: All 24-bits are transferred in parallel)

0 : Transfer CNTR to OL

1

(Note: All 24-bits are transferred in parallel)

1 : Transfer PR0 to PSC

1

7266R1-111196-2

0

: Select RLD

0

0 : Select the RLD addressed by X/Y input

1 : Select both XRLD and YRLD together

(Note: D7 = 1 overrides X/Y input)

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