GS9020 데이터 시트보기 (PDF) - Gennum -> Semtech
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GS9020 Datasheet PDF : 30 Pages
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DETAILED DESCRIPTION
The GS9020 EDH coprocessor consists of five major
blocks:
1. Data Input/Output Block (with automatic standard
detect)
2. Flywheel Block
3. EDH Block
4. Data Processing Block
5. Host Interface (HOSTIF) Block
The following convention is used to differentiate device pins
from HOST interface table bits.
PIN
LOGIC OPR
HOSTIF
XX
YY
SDI/SDI and SCI/SCI are high speed Pseudo-ECL (PECL)
compatible differential inputs with internal pullup resistors
(75Ω nominally) as shown in Figure 4. Note that each pullup
resistor has a dedicated power pin allowing the use of other
interfacing topologies.
The internal pullup resistors allow the GS9020 to be easily
interfaced to the GS9025 as shown in Figure 5 and Figure
17. An external diode is required to offset the input signals
to the input range of the GS9020. For maximum signal
integrity the GS9025 and GS9020 should be placed as
close together as possible.
The PECL serial input signals are first converted to CMOS
levels and then deserialized to 10 bit parallel format (based
on the TRS headers), descrambled, and then passed to the
processing core.
1.2 Parallel Digital Video Data Outputs
LOGIC OPR (logic operator) gives the combinational
relationship (if one exists), between pins which also have a
corresponding HOST bit. This operator governs the signal
the GS9020 receives. The following is the list of possible
logic operators and their meaning.
LOGIC OPR
AND
OR
>
<
MEANING
XX AND YY
XX OR YY
XX takes precedence over YY
YY takes precedence over XX
PIN
DOUT[9:0]
LOGIC OPR
HOST BIT
The output of the device is 10-bit digital video data and is
present on the DOUT[9:0] output pins.
1.3 Reserialized Data Output
PIN
SDO, SDO
SDOMODE
LOGIC OPR
HOST BIT
1. DATA INPUT/OUTPUT BLOCK
1.1 Serial Video Data Inputs
PIN
SDI, SDI
SCI, SCI
LOGIC OPR
HOST BIT
Serial data and clock signals are supplied to the GS9020
chip via the SDI/SDI and SCI/SCI pins, respectively. Eight
standards are supported: Composite, 4:2:2 Component with
13.5MHz Y sampling, 4:2:2 16 x 9 wide screen with 18MHz
Y sampling, and 4:4:4:4 Component Single Link with
13.5MHz Y sampling, all in both NTSC and PAL formats.
See Table 1.
The GS9020 also provides PECL differential serial data
outputs (SDO/SDO). The serial data outputs can operate in
one of two modes as controlled by the SDOMODE pin.
When SDOMODE is set LOW, re-serialized processed data
is output at the SDO/SDO output pins.
When SDOMODE is set HIGH, the serial input data is
supplied directly to the SDO/SDO output pins, bypassing
the processing core. After changing SDOMODE, the
GS9020 must be reset for proper operation.
The serial data output circuits are shown in Figure 6. The
serial data outputs are designed to drive 50-75Ω controlled
impedance traces and can be easily connected to the
GS9028 cable driver as shown in Figure 7 and Figure 18.
Note that to output proper PECL signal levels, a resistor
must be connected between the two serial data outputs.
7
521 - 66 - 05
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