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LV3329PE 데이터 시트보기 (PDF) - SANYO -> Panasonic

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LV3329PE
SANYO
SANYO -> Panasonic SANYO
LV3329PE Datasheet PDF : 30 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Continued from preceding page.
Pin No.
Pin name
23
LFOUT
22
LROUT
11
RFOUT
12
RROUT
LV3329PE
Function
Fader output pins.Attenuation is possible
separately for the front end and rear end.
42
Vref
Connect a capacitor of a few tens of μF
between Vref and AVSS (VSS) as a 0.5 × VDD
voltage generator, current ripple
countermeasure.
36
VREG
Internal logic voltage pin.
37
VDD
13
DVSS
21
AVSS
38
MUTE
Power supply pin.
Logic ground pin.
Analog ground pin.
External muting control pin.
Setting this pin to VSS level sets forcibly fader
volume block to -level.
40
TIM
18
CL
19
DI
20
CE
16
TEST3
15
TEST4
14
TEST5
41
TEST1
39
TEST2
17
OSC
Timer pin when there is no signal in the zero
cross circuit.Forcibly set data when there is no
zero cross signal, from the time the data is set
until the timer ends.
Input pin for serial data and clock used for
control.
Chip enable pin.Data is written to the internal
latch and the analog switches are operated
when the level changes from High to Low. Data
transfer is enabled when the level is High.
Connect to VSS
Normally this pin is OPEN.
IC test pin.
Normally this pin is OPEN.
External oscillat input pin.
Equivalent Circuit
VDD
- 200Ω
+
-
20kΩ
+
20kΩ
LVref
RVref
-
100kΩ
+
100kΩ
VREG
VDD
VDD
VDD
50kΩ
1kΩ
VDD
VREG
930kΩ
VDD
1kΩ
VDD
No.A1856-9/30

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