M12L16161A-5TIG 데이터 시트보기 (PDF) - [Elite Semiconductor Memory Technology Inc.

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M12L16161A-5TIG

512K x 16Bit x 2Banks Synchronous DRAM

[Elite Semiconductor Memory Technology Inc. 

ESMT

M12L16161A

Operation temperature condition -40℃~85℃

Read & Write Cycle at Same Bank @Burst Length = 4

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

tRCD

tRC *Note1

HIGH

*Note2

ADDR

Ra

Ca0

Rb

Cb0

BA

A10/AP

Ra

CL=2

QC

CL=3

WE

DQM

tRAC

*Note3

tRAC

*Note3

Rb

tOH

Qa0 Qa1

tSAC

Qa2

tOH

Qa3

tS HZ *Note4

Qa0 Qa1 Qa2 Qa3

tSAC

tS HZ *Note4

Db0 Db1 Db2 Db3

tRDL

Db0 Db1 Db2 Db3

tRDL

Row Active

(A-Bank)

Read

(A- Ban k)

Precharge

(A- Ban k)

Row Active

(A-Bank)

Write

(A-Bank)

Precharge

(A- Ban k)

: Don't care

*Note: 1.Minimum row cycle times is required to complete internal DRAM operation.

2.Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row

precharge. Last valid output will be Hi-Z(tSHZ) after the clock.

3.Access time from Row active command. tcc*(tRCD +CAS latency-1)+tSAC

4.Ouput will be Hi-Z after the end of burst.(1,2,4,8 bit burst)

Burst can’t end in Full Page Mode.

Elite Semiconductor Memory Technology Inc.

Publication Date : May. 2007

Revision : 1.1

14/29

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