M64893AFP 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC
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M64893AFP Datasheet PDF : 12 Pages
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MITSUBISHI BIPOLAR DIGITAL ICs
M64893AFP/AGP
SERIAL INPUT PLL FREQUENCY SYNTHESIZER FOR TV/VCR
Test mode data set up method
The data for the test mode uses 20 to 27bits. Data is latched when the 27th clock signal falls.
(1) When transferring 3-wire 27 bit data
ENA
CLK
1
BAND SW
DATA
M COUNTER DIVISION
RATIO SETTING
19 20
27
S COUNTER
DIVISION RATIO
SETTING
SI CP T2 T1 TO RSa RSbOS
TEST DATA SETTING
READ INTO LATCH
(2) Test Mode Bit Set Up
X
:Random, 0 or 1.normal "0"
CP
:Set up the charge pump current value
T0, T1,&T2 :Set up test modes
RSa, Rsa
:Set up for the reference Frequency division ratio
OS
:Set up the tuning amplifier
SI
:1 Only (It is prohibit to "0 ")
Setting up the charge pump current of the phase comparator
CP Charge pump current
0
70 uA
1
270 uA
Mode
Test
Normal
Setting up for the test mode
T2 T1 T0
0 0X
0 1X
1 10
1 11
1 00
1 01
Charge pump
Normal operation
High impedance
Sink
Source
High impedance
High impedance
12 pin output
LD
LD
LD
LD
fREF
f1/N
Mode
Normal operation
Test mode
Test mode
Test mode
Test mode
Test mode
MITSUBISHI
4 -12
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