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930104701(2007) 데이터 시트보기 (PDF) - Atmel Corporation
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930104701
(Rev.:2007)
Rad. Tolerant 128K x 8 5-volts Very Low Power CMOS SRAM
Atmel Corporation
930104701 Datasheet PDF : 16 Pages
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Write Cycle 3 CS1 or CS2,
Controlled
M65608E
Note:
The internal write time of the memory is defined by the overlap of CS1 Low and CS2 HIGH and W LOW. Both signals must be
actived to initiate a write and either signal can terminate a write by going in actived. The data input setup and hold timing should
be referenced to the actived edge of the signal that terminates the write. Data out is high impedance if OE =
V
IH
.
10
4151M–AERO–07/07
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