M65665CFP 데이터 시트보기 (PDF) - Renesas Electronics
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M65665CFP Datasheet PDF : 18 Pages
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M65665CFP/SP
I2C Register Information
When using any or all of the information contained in this table, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products.
Address
00h
01h
02h
03h
04h
05h
06h
Bit
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
<7:0>
<7:0>
<7>
<6:0>
<7>
<6:0>
<7>
<6>
<5:0>
<7:6>
Symbol
DISP
SIZE_V
SIZE_H
WEN
BGC
BGCS
FREE_RUN
VXA<7:0>
HXA<7:0>
DECODE
CONTRAST<6:0>
KILLER
U_DAC<6:0>
GRC
YUVN_RGB_SEL
TINT<5:0>
EXT_SC_SEL<1:0>
<5:4> DCONT<1:0>
<3:0> HT<3:0>
07h
<7:6> INPUT_SEL<1:0>
<5:0> BG_START<5:0>
08h
<7:4> ADJ<3:0>
<3:0> YDL<3:0>
09h
<7:5> BGBY<2:0>
<4:0> Y_OFFSET<4:0>
0Ah
<7> VCHIP ONLY
<6:4> BGRY<2:0>
<3:0> BGY<3:0>
0Bh
<7:4> PEDESTV<3:0>
<3:0> PEDESTU<3:0>
Read/
Write
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
Reset
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1/9 Ref.
Value
1h
0
0
1h
0
0
0
0
20h
20h
0
32h
0
32h
1h
0
0
1h
W/R 0
0
W/R 0
Ah
W/R 0
2h
W/R 0
0Fh
W/R 0
4h
W/R 0
Ah
W/R 0
0
W/R 0
0Fh
W/R 0
1h
W/R 0
0
W/R 0
6h
W/R 0
0
W/R 0
0
Remarks
Sub picture display : [0] off , [1] on
Sub picture vertical size : [0] 1/9 , [1] 1/16
Sub picture horizontal size : [0] 1/9 , [1] 1/16
Sub picture : [0] Still , [1] Moving
Back ground display : [0] off , [1] on
Sub picture mute : [0] off , [1] on
VCXO oscilation : [0] Lock , [1] Free run
For test : 0 set only
Sub picture vertical position
Sub picture horizontal position
Sub picture color decoder reset : [1] reset
Sub picture Y or R DAC output amplitude control
Sub picture color killer : [0] enable , [1] disable
Sub picture U or G DAC output amplitude control
Frame display : [0] off , [1] on
PIP output mode selection : [0] YUV , [1] RGB
Sub picture TINT control
Sub picture c-sync sep. selection :
[0] int. digital , [1] int. auto slice , [2] ext.(18 pin) , [3] int.
analog
Sub picture int. c-sync sep. threshhold setting.
Sub picture display timing adjust
Sub picture input selection : [0] YC , [1] N.A. , [2] CVBS , [3]
YUV
Sub picture Burst Gate Pulse position setting
Main/Sub switch delay control
Sub picture Y/C delay adjust
Back ground U level setting
Sub picture Y bright control
V-chip decode mode : [0] off , [1] on
Back ground V level setting
Back ground Y level setting
Sub picture V pedestal level (2's comp)
Sub picture U pedestal level (2's comp)
Rev.2.00, Sep.04.2003, page 9 of 17
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