M65667FP 데이터 시트보기 (PDF) - Renesas Electronics

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M65667FP

PICTURE-IN-PICTURE SIGNAL PROCESSING

Renesas Electronics 

M65667FP

Block Diagram

CSYNC (s) BGP (s)

SCK

/TEST1

/TEST0

Yin

Sync tip

clamp

Cin

Bias

Vdd/Vss 15

For test 3

DATA 3 I2C

CLK

I/F

ACK

Vin (s)

Sync tip

A/D

8 bit

clamp

V-chip

data slicer

Y/C SEP

(LPF, BPF)

Vrt (m)

2

Vrb (m)

HD

ADJ-Ysub

(I2C)

Phase

select

HPLL 4 fsc

Luma

Y

clamp

Sync

sep

C

Demod

Yout-sub

D/A

8 bit

D/A

Cout-sub

8 bit

Delay

fsc

Delay

MIX

ADJ-Csub

Vin (m)

Bias

A/D

8 bit

Level

detect

Burst data

sampling

Vrt (m)

2

Vrb (m)

RAM (1H)

Delay

Y6

AFC

Tint

Timing gen

(Decode)

B-Y 6

R-Y 6

Delay

LPF

&MPY

6Y

6 B-Y

6 R-Y

Vert-filter

&

MUX

Y

B-Y

R-Y

RAM

96 Kbits

Phase

detect

Lock/Free-run

via I2C

VCXO

driver

Y-PlP

C-PlP

Bias C-PlPin

Back porch

clamp

Y-PlPin

SWMG

/TEST7

Timing gen

(Memory

cont)

4 fsc

VCXO

VD

/CSYNC

/TEST6

HD

/TEST5

FILTER

BIAS

VCXO in

VCXO out

RESET

MCK

BGP (m)

/TEST2

fsc

/TEST3

SWM

/TEST4

REJ03F0185-0201 Rev.2.01 Mar 31, 2008

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