MX29F8100 데이터 시트보기 (PDF) - Macronix International

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MX29F8100

8M-BIT [1M x 8/512K x 16] CMOS SINGLE VOLTAGE FLASH MEMORY

Macronix International 

INDEX

MX29F8100

HARDWARE SECTOR PROTECTION

The MX29F8100 features sector protection. This feature

will disable both program and erase operations in either

the top or the bottom sector (0 or 7). The sector protection

feature is enabled using system software by the

user(Refer to table 3). The device is shipped with both

sectors unprotected. Alternatively, MXIC may protect

sectors in the factory prior to shipping the device.

SECTOR PROTECTION

To activate this mode, a six-bus cycle operation is

required. There are two 'unlock' write cycles. These are

followed by writing the 'set-up' command. Two more

'unlock' write cycles are then followed by the Lock Sector

command - 20H. Sector address is latched on the falling

edge of CE or WE of the sixth cycle of the command

sequence. The automatic Lock operation begins on the

rising edge of the last WE pulse in the command

sequence and terminates when the Status on DQ7 is '1'

at which time the device stays at the read status register

mode.

The device remains enabled for read status register

mode until the CIR contents are altered by a valid

command sequence (Refer to table 3,6 and Figure 10,12

).

VERIFY SECTOR PROTECT

To verify the Protect status of the Top and the Bottom

sector, operation is initiated by writing Silicon ID read

command into the command register. Following the

command write, a read cycle from address XXX0H

retrieves the Manufacturer code of C2H. A read cycle

from XXX1H returns the Device code 88H. A read cycle

from appropriate address returns information as to which

sectors are protected. To terminate the operation, it is

necessary to write the read/reset command sequence

into the CIR.

(Refer to table 3,4 and Figure 12)

A few retries are required if Protect status can not be

verified successfully after each operation.

SECTOR UNPROTECT

It is also possible to unprotect the sector , same as the first

five write command cycles in activating sector protection

mode followed by the Unprotect Sector command - 40H,

the automatic Unprotect operation begins on the rising

edge of the last WE pulse in the command sequence and

terminates when the Status on DQ7 is '1' at which time the

device stays at the read status register mode.(Refer to

table 3,6 and Figure 11,12)

The device remains enabled for read status register

mode until the CIR contents are altered by a valid

command sequence.

Either Protect or Unprotect sector mode is accomplished

by keeping WP high, i.e. protect-bit status can only be

changed with a valid command sequence and WP at high.

When WP is high, all sectors can be programmed or

erased regardless of the state of the protect-bits. Protect-

bit status will not be changed during chip/sector erase

operations. With WP at VIL, only unprotected sectors

can be programmed or erased.

DEEP POWER-DOWN MODE

The MXIC's 8Mbit flash family supports a typical ICC of

1uA in deep power-down mode. One of the target markets

for these devices is in protable equipment where the

power consumption of the machine is of prime

importance. When PWD is a logic low (GND ± 0.2V), all

circuits are turned off and the device typically draws 1uA

of ICC current.

During read modes, the PWD pin going low deselects the

memory and places the output drivers in a high

impedance state. Recovery from the deep power-down

state, requires a minimum of 700 nanoseconds to access

valid data.

During erase or program modes, PWD low will abort

either erase or program operation. The contents of the

memory are no longer valid as the data has been

corrupted by the PWD function. As in the read mode

above, all internal circuitry is turned off to achieve the 1uA

current level.

PWD transitions to VIL or turning power off to the device

will clear the status register.

PWD pin is not provided in 44-pin SOP package.

P/N: PM0262

REV. 2.0, JAN. 22, 1999

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