MX29L1611PC-10 데이터 시트보기 (PDF) - Macronix International

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MX29L1611PC-10

16M-BIT [2M x 8/1M x 16] CMOS SINGLE VOLTAGE FLASH EEPROM

Macronix International 

MX29L1611G / MX29L1611*

CLEAR STATUS REGISTER

The Eraes fail status bit (Q5) and Program fail status bit

(Q4) are set by the write state machine, and can only be

reset by the system software. These bits can indicate

various failure conditions(see Table 6). By allowing the

system software to control the resetting of these bits,

several operations may be performed (such as

cumulatively programming several pages or erasing

multiple blocks in squence). The status register may

then be read to determine if an error occurred during that

programming or erasure series. This adds flexibility to

the way the device may be programmed or erased.

Additionally, once the program(erase) fail bit happens,

the program (erase) operation can not be performed

further. The program(erase) fail bit must be reset by

system software before further page program or sector

(chip) erase are attempted. To clear the status register,

the Clear Status Register command is written to the CIR.

Then, any other command may be issued to the CIR.

Note again that before a read cycle can be initiated, a

Read command must be written to the CIR to specify

whether the read data is to come from the Array, Status

Register or Silicon ID.

P/N:PM0604

REV. 0.8, JAN. 24, 2002

11

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