NT5SV16M4DT 데이터 시트보기 (PDF) - Unspecified

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NT5SV16M4DT

64Mb Synchronous DRAM

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NT5SV16M4DT

NT5SV8M8DT

NT5SV4M16DT

64Mb Synchronous DRAM

Burst Mode Operation

Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations

(read cycle). There are three parameters that define how the burst mode will operate. These parameters include burst

sequence, burst length, and operation mode. The burst sequence and burst length are programmable, and are determined by

address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is set by address bits

A7 - A11, BS0, and BS1.

The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM. Two types of burst

sequences are supported, sequential and interleaved. See the table below.

The burst length controls the number of bits that will be output after a Read Command, or the number of bits to be input after a

Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 or full page(actual page length is dependent

on organization: x4, x8, or x16).Full page burst operation is only posible using the sequential burst type.

Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation implies that the

device will perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple burst with

single write operation was added to support Write Through Cache operation. Here, the programmed burst length only applies to

read cycles. All write cycles are single write operations when this mode is selected.

Burst Length and Sequence

Burst Length

2

4

8

Full Page(Note)

Starting Address (A2 A1 A0)

xx0

xx1

x00

x01

x10

x11

000

001

010

011

100

101

110

111

nnn

Sequential Addressing (decimal)

0, 1

1, 0

0, 1, 2, 3

1, 2, 3, 0

2, 3, 0, 1

3, 0, 1, 2

0, 1, 2, 3, 4, 5, 6, 7

1, 2, 3, 4, 5, 6, 7, 0

2, 3, 4, 5, 6, 7, 0, 1

3, 4, 5, 6, 7, 0, 1, 2

4, 5, 6, 7, 0, 1, 2, 3

5, 6, 7, 0, 1, 2, 3, 4

6, 7, 0, 1, 2, 3, 4, 5

7, 0, 1, 2, 3, 4, 5, 6

Cn, Cn+1, Cn+2, .....

Note: Page length is a function of I/O organization and column addressing.

x4 organization (CA0-CA9); Page Length = 1024 bits

x8 organization (CA0-CA8); Page Length = 512 bits

x16 organization (CA0-CA7); Page Length = 256 bits

Interleave Addressing (decimal)

0, 1

1, 0

0, 1, 2, 3

1, 0, 3, 2

2, 3, 0, 1

3, 2, 1, 0

0, 1, 2, 3, 4, 5, 6, 7

1, 0, 3, 2, 5, 4, 7, 6

2, 3, 0, 1, 6, 7, 4, 5

3, 2, 1, 0, 7, 6, 5, 4

4, 5, 6, 7, 0, 1, 2, 3

5, 4, 7, 6, 1, 0, 3, 2

6, 7, 4, 5, 2, 3, 0, 1

7, 6, 5, 4, 3, 2, 1, 0

Not Supported

REV 1.1

10/01

7

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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

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