NVM3060 데이터 시트보기 (PDF) - Unspecified

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NVM3060

4096-Bit EEPROM

Unspecified 

NVM 3060

Block

programming

enable

Read

reference

shift -0.3 V

Test Byte

enable

Read

reference

shift -0.6V

7

6

5

4

Fig. 4–1: Functions of the 8 bits in the test byte

Charge

Pump

disable

3

Read

reference

shift + 0.3 V

2

Read

reference

shift + 0.6 V

1

0

4. Test Functions

This description of the test byte is not part of the specifi-

cation. It contains no information necessary for normal

(intended) use of the NVM 3060 memory. It is only in-

tended as a description of the various functions of the

test byte that are designed for factory use, but it does not

specify such properties. The description is subject to

change.

Address location 516 contains a test byte which governs

test mode operation of the NVM 3060. The test byte is

set by performing the IM bus operation for entering ad-

dress 516, followed by an IM bus programming opera-

tion with the desired test data word. The test byte is valid

during all following IM bus operations until changed or

set to 0 by a Reset = L signal. The test byte shall not be

changed during the busy time of a programming opera-

tion. Fig. 4–1 shows the bit arrangement of the test byte.

Set bit 5 for activation of the test byte!

4.1. Block Programming

Three block program modes can be activated by the test

byte, in conjunction with the memory address loaded

into the memory address register:

memory address

987654 3 21 0

1) all bytes are selected : 0 x x x x x x x 0 x (e.g. 0)

2) all even-numbered

bytes are selected : 0 x x x x x x x 1 0 (e.g. 2)

3) all odd-numbered

bytes are selected : 0 x x x x x x x 1 1 (e.g. 3)

Thus, programming all selected bytes with the same de-

sired data is done within one programming sequence.

The complete sequence is:

Enter Address 516

Program Test byte (e.g. 160)

Enter Address 0, 2 or 3

Program Data

A checkerboard pattern is programmed with two pro-

gramming operations after loading the test byte:

Enter Address 2

Program Data 85

Enter Address 3

Program Data 170

4.2. Read Reference Shifting

During read operations the memory cell threshold volt-

age is compared with a reference voltage. The com-

parator output then produces the logic one level for a cell

threshold higher than the reference and the logic zero

level for a cell threshold lower than the reference.

The test byte provides means to shift the reference volt-

age in positive or negative direction in three steps:

±0.3 V, ±0.6 V, and ±0.9 V.

During a read operation a positive-shifted reference

voltage establishes a margin test for logic ones,

whereas a negative-shifted reference does so for logic

zeroes. This margin test is performed digitally by IM bus

operations only, without the need to switch analog power

supplies.

+0.9V :

+0.6V :

+0.3V :

-0.3V :

-0.6V :

-0.9V :

7654 3 21 0

x 0 1 0 x1 x1

x 0 1 0 x0 x1

x 01 0 x1 x0

x11 0 x0x0

x01 1 x0x0

x11 1 x0x0

4.3. Charge Pump Disable

Bit 3 of the test byte disables the high voltage charge

pump.

9

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