PI6C103L 데이터 시트보기 (PDF) - Pericom Semiconductor

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PI6C103L

Precision Clock Synthesizer for Mobile PCs

Pericom Semiconductor 

PI6C103

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Pin Description

28-Pin Package

Type

Pin

Qty.

Symbol

Description

2

1 Input XTAL_IN 14.318 MHz crystal input

3

1 Output XTAL_OUT 14.318 MHz crystal output

4

1 Output PCICLK_F 3.3V free running PCI clock output

5,6,9,10,11 5 Output PCICLK[1-5] 3.3V PCI Clock outputs

13

1 Output

48MHz 3.3V 48MHz clock output

14

1

Output

48-24MHz/TS#

3.3V 48 or 24MHz output and Hi-Z state strapping option(2,5)

Strap Low = Enter Hi-Z state mode for testing, Strap High = Normal operation

16

1

Input

SEL100/66#

Select for enabling 100 MHz or 66 MHz CPU clock(5)

H = 100 MHz, L = 66 MHz

17

1 Input PWR_DWN# Device enters power down mode when LOW5

18

1 Input CPU_STOP# When Low, stop CPU clocks in LOW state

20

1 Input PCI_STOP# When signal LOW, stops all PCI clocks in LOW state except for PCICLK_F output(5)

23,24

2 Output CPUCLK[1-0] 2.5V CPU clock outputs

3.3V 14.318 MHz reference clock output and power-on spread spectrum

26

1

Output

REF0/Spread#

enable strap option(3,5)

Strap Low = Spread spectrum clocking enable

Strap High = Spread spectrum clocking disable

3.3V 14.318 MHz reference clock output and power-on 48/24 MHz

27

1

Output

REF1/SEL48#

select strap option4,5

Pin 14 output = 48 MHz when straped LOW

Pin 14 output = 24 MHz when strapped HIGH

8,12,19,28

1,7,15,21

25

22

1 Power

Power

1 Power

1 Power

VDD

VSS

VDD2

VSS2

3.3V Power

3.3V Ground

2.5V Power

2.5V Ground

Notes:

1. VDD and VSS names in the above table reflect a likely internal power and ground partition to reduce the effects of internal noise on the performance

of the device. In reality, the platform will be configured with the same voltage VDD pins tied to a common supply and all VSS pins being common.

The VDD/VSS naming convention above is done to show how the pinout is dominated by the need to isolate all the signals.

2. The output frequency at this pin is dependent on the power on strapping option at pin 27. A 48 MHz output when power-on strapped LOW,

and 24 MHz output when strapped HIGH. This pin also serves as Hi-Z state strapping option during power-on configuration. During power-on,

the PI6C103 will sample the value at this pin. Strapped LOW for Hi-Z state mode and HIGH for normal operation.

3. This is a dual function pin. During power-on, all clock outputs are disabled, and the PI6C103 will sample the spread spectrum enable/disable strapping

option. After the strapped value latches, all clock outputs will be enabled simultaneously and this pin will become a 14.318 MHz reference clock

output. The Power-on latency needs to be less than 3ms after the supply voltage stabilized.

4. This is a dual function pin. During power-on, all clocks are disabled, and PI6C103 will sample the SEL48# strapping option. After the strapped

value latches, all clock outputs will be enabled simultaneously and this pin will become another 14.318 MHz reference clock output. The power-

on latency needs to be less than 3ms after the supply voltage stabilized.

5. Internally pulled up with resistor min.value of 50kΩ.

223

PS8315-2 04/08/99

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