SP8854E 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc

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SP8854E

2.7GHz Parallel Load Professional Synthesiser

Zarlink Semiconductor Inc 

SP8854E Preliminary Information

STROBE

CONTROL

MICRO

SP8854E

27 28

33p

100p

10MHZ

Application using

crystal reference

15V

15V

1n

1n

1n

1k

7 6 5 4 3 2 1 44 43 42 41 4039

8

38

9

37

10

36

11

35

12

SP8854E

34

13

33

14

32

15

31

16

30

17

29

18 19 20 21 22 23 24 25 26 27 28

100p

LOOP FILTER

*

**

130V

15V

2·2k

1µ

10n

15V

1n

REF IN

FREF

FPD

VCO

OP27

ETC

* VALUES DEPEND

ON APPLICATION

Figure 5 - Typical application diagram

Description

Prescaler and AM counter The programmable divider

chain is of A and M counter construction and therefore

contains a dual modulus front end prescaler, an A counter

which controls the dual modulus ratio and an M counter

which performs the bulk multi-modulus division. A program-

mable divider of this construction has a division ratio of

MN1A and a minimum integer steppable division ratio of

N(N21), where N is the prescaler value.

Data Entry and Storage

Data is loaded from the 16-bit bus into one of the internal

buffers by applying a positive pulse to the STROBE input.

The input bus can be driven from TTL or CMOS logic

levels. When STROBE is low, the inputs are isolated and the

data can be changed without affecting the programmed

state.

When STROBE input is taken high, the A and M counters

are reset and the input data is applied to the internal storage

register. When the STROBE input is again taken low, the

data on the input bus is stored in the internal storage register

and the A and M counters released. The STROBE input is

level triggered so that if the data is changed whilst the input

is high, the final value before STROBE goes low will be

stored.

In order to prevent disturbances on the VCO control voltage

when frequency changes are made, the STROBE input

disables

6

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