AD6458 데이터 시트보기 (PDF) - Analog Devices

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AD6458

GSM 3 V Receiver IF Subsystem

Analog Devices 

AD6458

2.0

1.9

TA = –40°C

1.8

1.7

TA = –25°C

1.6

1.5

TA = +25°C

1.4

1.3

TA = +85°C

1.2

1.1

1.0

0

0.5

1.0

1.5

2.0

2.5

VGAIN – Volts

Figure 29. Minimum Power-Up Voltage vs VGAIN, VPOS =

3.0 V, VREF = 1.2 V

PRODUCT OVERVIEW

The AD6458 provides most of the active circuitry required to

realize a complete low power, single-conversion superhetero-

dyne receiver, or the latter part of a double-conversion receiver,

at input frequencies up to 400 MHz, with an IF from 5 MHz to

50 MHz. The internal I/Q demodulators, and their associated

phase-locked loop, support a wide variety of modulation modes,

including n-PSK, n-QAM, and GMSK. A single positive supply

voltage of 3.3 V is required (3.0 V minimum, 3.6 V maximum)

at a typical supply current of 9 mA at midgain. In the following

discussion, VPOS will be used to denote the power supply volt-

age, which will be assumed to be 3.3 V.

Figure 31 shows the main sections of the AD6458. It consists of

a variable-gain UHF mixer and linear two-stage IF strip, which

together provide a calibrated voltage-controlled gain range of

more than 76 dB, followed by dual quadrature demodulators.

These are driven by inphase and quadrature clocks generated by

a Phase-Locked Loop (PLL), which is locked to a corrected

external reference. A CMOS-compatible power-down interface

completes the AD6458.

Mixer

The UHF mixer is an improved Gilbert-cell design, and can

operate from low frequencies (it is internally dc-coupled) up to

an RF input of 400 MHz. The dynamic range at the input of the

mixer is determined at the upper end by the maximum input

signal level of ± 56 mV (–15 dBm in 50 Ω between RFHI and

RFLO) up to which the mixer remains linear and, at the lower

end, by the noise level. It is customary to define the linearity of

a mixer in terms of the 1 dB gain-compression point and third-

order intercept, which for the AD6458 are –12 dBm and

–2 dBm, respectively, in a 50 Ω system.

The mixer’s RF input port is differential; that is, pin RFLO is

functionally identical to RFHI, and these nodes are internally

biased. The RF port can be modeled as a parallel RC circuit as

shown in Figure 30.

RFHI

RFLO

CSH

RSH

Figure 30. Mixer Port Modeled as a Parallel RC Network

The local oscillator (LO) input is internally biased at VP – 0.8 V

and must be ac coupled. The LO interface includes a preampli-

fier which minimizes the drive requirements, thus simplifying

the oscillator design and reducing LO leakage from the RF port.

The LO requires a single-sided drive of ± 50 mV, or –16 dBm in

a 50 Ω system. For operation above 300 MHz noise figure can

be improved by increasing the LO level.

The output of the mixer is single ended with a 330 Ω impedance

for driving ceramic filters.

The conversion gain is measured between the mixer input and

the input of this filter, and varies between –9 dB and +10 dB as

a function of the voltage at Pin GAIN.

The maximum permissible signal level at Pin MXOP is deter-

mined by the maximum gain control voltage.

The mixer output port is shown in Figure 32.

LO INPUT

–16dBm

LOIP

4

RF INPUT RFHI 6

–95dBm TO

–15dBm RFLO 5

VPS1 20

VPS2 18

PRUP 3

MXOP

9

13MHz

CERAMIC

BANDPASS

FILTER

330Ω

0.1µF

11 IFIP

12

IFIM

AGC VOLTAGE

BIAS

CIRCUIT

2

COM1

7

COM2

AD6458

0°

PLL

90°

4.7kΩ

17 IRXP

16 IRXN

4.7kΩ

1 FREF

19 FLTR

4.7kΩ

15 QRXP

14 QRXN

4.7kΩ

GAIN TC

COMPENSATION

13 GAIN

8 GREF

Figure 31. Functional Block Diagram

–10–

REV. 0

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