HIP4020(1997) 데이터 시트보기 (PDF) - Intersil

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HIP4020
(Rev.:1997)

Half Amp Full Bridge Power Driver for Small 3V, 5V and 12V DC Motors

Intersil 

HIP4020

Application

The HIP4020 is designed to detect load current feedback from

sampling resistors of low value in the source connections of the

output drivers to VDD, VSSA and VSSB (See Figure 1). When the

sink or source current at OUTA or OUTB exceeds the preset

OC (Over-Current) limiting value of 550mA typical, the current

is held at the limiting value. If the OT (Over-Temperature) Shut-

down Protection limit is exceeded, temperature sensing BiMOS

circuits limit the junction temperature to 150oC typical.

The circuit of Figure 1 shows the Full H-Switch in a small motor-

drive application. The left (A) and right (B) H-Switch’s are con-

trolled from the A and B inputs via the A and B CONTROL

LOGIC to the MOS output transistors Q1, Q2, Q3 and Q4. The

circuit is intended to safely start, stop, and control rotational

direction for a motor requiring no more than 0.5A of supply cur-

rent. The stop function includes a Dynamic Braking feature.

With the ENABLE Inputs Low, the MOS transistors Q1 and Q3

are OFF; which cuts-off supply current to OUTA and OUTB.

With the BRAKE terminal Low and ENABLE Inputs High, either

Q1 and Q4 or Q3 and Q2 will be driven into conduction by the

DIRECTION Input Control terminal. The MOS output transistor

pair chosen for conduction is determined by the logic level

applied to the DIRECTION control; resulting in either clockwise

(CW) or counter-clockwise (CCW) shaft rotation.

When the BRAKE terminal is switched high (while holding

the ENABLE input high), the gates of both Q2 and Q4 are

driven high. Current flowing through Q2 (from the motor ter-

minal OUTA) at the moment of Dynamic Braking will con-

tinue to flow through Q2 to the VSSA and VSSB external

connection, and then continue through diode D4 to the motor

terminal OUTB. As such, the resistance of the motor winding

(and the series-connected path) dissipates the kinetic

energy stored in the system. Reversing rotation, current

flowing through Q4 (from the motor terminal OUTB), at the

moment of Dynamic Braking, would continue to flow through

Q4 to the VSSB and VSSA tie, and then continue through

diode D2 to the motor terminal OUTA, to dissipate the stored

kinetic energy as previously described.

Where VDD to VSS are the Power Supply reference terminals

for the Control Logic, the lowest practical supply voltage for

proper logic control should be no less than 2.0V. The VSSA

and VSSB terminals are separate and independent from VSS

and may be more negative than the VSS ground reference

terminal. However, the maximum supply level from VDD to

VSSA or VSSB must not be greater than the Absolute Maxi-

mum Supply Voltage rating.

Terminals A1, B1, A2, B2, ENA and ENB are internally con-

nected to protection circuits intended to guard the CMOS

gate-oxides against damage due to electrostatic discharge.

(See Figure 3) Inputs ENA, ENB, A1, B1 A2 and B2 have

CD74HCT4000 Logic Interface Protection and Level Con-

verters for TTL or CMOS Input Logic. These inputs are

designed to typically provide ESD protection up to 2kV. How-

ever, these devices are sensitive to electrostatic discharge.

Proper I.C. handling procedures should be followed.

VDD

INPUT

LEVEL

CONV.

FIGURE 3. LOGIC INPUT ESD INTERFACE PROTECTION

VDD

A1

(DIR)

A2

(BRAKE)

P-DR

LIMIT

Q1

OT AND OC

PROTECT

Q2

D1

OUTA

D2

ENA

(ENABLE)

N-DR

LIMIT

VSSA

VDD

B1

(DIR)

B2

(BRAKE)

P-DR

LIMIT

Q3

OT AND OC

PROTECT

Q4

D3

OUTB

D4

ENB

(ENABLE)

N-DR

LIMIT

VSSB

FIGURE 4. EQUIVALENT CONTROL LOGIC A AND B SHOWN DRIVING THE OUTA AND OUTB OUTPUT DRIVERS

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