HIP4020 데이터 시트보기 (PDF) - Intersil
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HIP4020 Datasheet PDF : 9 Pages
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HIP4020
Electrical Specifications
PARAMETER
Thermal Shutdown
Response Time: VEN to VOUT
Turn-On: Prop Delay
Rise Time
Turn-Off: Prop Delay
Fall Time
TA = 25°C, VDD = +5V, VSSA = VSSB = VSS = 0V, Unless Otherwise Specified (Continued)
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
TSD
tPLH
IO = 0.5A (Note 3)
-
145
-
-
2.5
-
tr
tPHL
tf
-
4
-
-
0.1
-
-
0.1
-
UNITS
°C
µs
µs
µs
µs
Pin Descriptions
PIN NUMBER
12, 19
15
16
6
8, 5
9, 3
7, 4
14, 17
2
SYMBOL
DESCRIPTION
VDD
VSSA
Positive Power Supply pins; internally common and externally connect to the same Positive Supply (V+).
Negative Power Supply pin; Negative or Ground return for Switch Driver A; externally connect to the Supply
(V-).
VSSB
Negative Power Supply pin; Negative or Ground return for Switch Driver B; externally connect to the Supply
(V-).
VSS
A1, B1
Common Ground pin for the Input Logic Control circuits. May be used as a common ground with VSSA and
VSSB .
Input pins used to control the direction of output load current to/from OUTA and OUTB, respectively. When
connected, A1 and B1 can be controlled from the same logic signal to change the directional rotation of a
motor.
A2, B2
Input pins used to force a low state on OUTA and OUTB, respectively. When connected, A2 and B2 can be
controlled from the same logic signal to activate Dynamic Braking of a motor.
ENA, ENB
Input pins used to Enable Switch Driver A and Switch Driver B, respectively. When Low, the respective
output is in a high impedance (Z) off-state. Since each Switch Driver is independently controlled, OUTA and
OUTB may be a separately PWM controlled as Half H-Switch Drivers.
OUTA, OUTB Respectively, Switch Driver A and Switch Driver B Output pins.
ILF
Current Limiting Fault Output Flag pin; when in a high logic state, signifies that Switch Driver A or B or both
are in a Current Limiting Fault Mode.
4
FN3976.3
December 20, 2005
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