STV0676 데이터 시트보기 (PDF) - STMicroelectronics

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STV0676

CMOS Digital Camera Co-processor

STMicroelectronics 

Overview

Figure 1: Block diagram of STV0676 video processor module

STV0676

CIF/VGA

Sensor

Video Processor

SDATA[4:0]

SSCL

SSDA

RESET_N

SCLK

SUSPEND

General purpose

housekeeper functions

including AEC, AGC and

AWB

SDA

SCL

RESET

STV0676

Video Compression (VC) Engine

Compressed Data

Stream Control +

FIFOs

USB core /glue

logic and

command FIFO’s

USB port

D+

D-

ROM RAM

10

Digiport

8052 Core

10

Clocks

+ PLL

12MHz

XTAL

GPIO/mode

select

Ext.

Interrupts

I2C Interface

1.2.2

Note:

Video processor functions

STV0676 provides a master clock SCLK to the camera module. Each 10-bit pixel value generated

by the sensor is transmitted across the 5 wire databus SDATA[4:0] as a pair of sequential 5-bit

nibbles, most significant nibble first. Codes representing the start and end frames and the start and

end of lines are embedded within the video data stream to allow the video processor to synchronise

with the video data stream.

The video processing engine performs the following functions on incoming data:

q full colour restoration at each pixel site from Bayer-patterned input data,

q matrixing/gain on each colour channel for colour purity,

q peaking for image clarity,

q gamma correction,

q colour space conversion from raw RGB to YCbCr[4:2:2].

The 2-wire sensor serial interface (SSDA and SSCL) provides control of sensor configuration.

the MSBit SDATA5 of the databus is unused in the current application but it will support future

sensors where a 12bit ADC architecture may be used.

6/21 Revision C

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