T14L256A 데이터 시트보기 (PDF) - Taiwan Memory Technology

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T14L256A

32K X 8 HIGH SPEED CMOS STATIC RAM

Taiwan Memory Technology 

tm TE

CH

T14L256A

Notes: 1. During this period, I/O pins are in the output state, so input signals of opposite phase to the

outputs should not be applied.

2. The data output from DOUT are the same as the data written to DIN during the write cycle.

3. DOUT provides the read data for the next address.

4. Transition is measured ± 500 mV from steady state with CL = 5pF. This parameter is

guaranteed but not 100% tested.

5. If OE is low during a WE controlled write cycle, the write pulse width must be the larger of

tWP or (tWHZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the

required tDW. If OE is high during a WE controlled write cycle, this requirement does

not apply and the write pulse can be as short as the specified tWP.

TM Technology Inc. reserves the right

P. 7

to change products or specifications without notice.

Publication Date: NOV. 2003

Revision: F

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