T5760-TG 데이터 시트보기 (PDF) - Atmel Corporation

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T5760-TG

UHF ASK/FSK Receiver

Atmel Corporation 

T5760 / T5761

0

–10

–20

–30

–40

–50

–60

–4 –3 –2 –1 0 1 2 3 4

df ( MHz )

Figure 6. Narrow band receiving frequency response

0

–20

–40

–60

–80

–100

–12 –9 –6 –3 0 3 6 9 12

df ( MHz )

Figure 7. Wide band receiving frequency response

Polling Circuit and Control Logic

The receiver is designed to consume less than 1 mA while

being sensitive to signals from a corresponding trans-

mitter. This is achieved via the polling circuit. This circuit

enables the signal path periodically for a short time.

During this time the bit-check logic verifies the presence

of a valid transmitter signal. Only if a valid signal is

detected the receiver remains active and transfers the data

to the connected µC. If there is no valid signal present the

receiver is in sleep mode most of the time resulting in low

current consumption. This condition is called polling

mode. A connected µC is disabled during that time.

All relevant parameters of the polling logic can be config-

ured by the connected µC. This flexibility enables the

user to meet the specifications in terms of current con-

sumption, system response time, data rate etc.

Regarding the number of connection wires to the mC, the

receiver is very flexible. It can be either operated by a

single bi-directional line to save ports to the connected mC

or it can be operated by up to five uni-directional ports.

Basic Clock Cycle of the Digital Circuitry

The complete timing of the digital circuitry and the

analog filtering is derived from one clock. This clock

cycle TClk is derived from the crystal oscillator (XTO) in

combination with a divide by 14 circuit. According to

chapter ‘RF Front End’, the frequency of the crystal oscil-

lator (fXTO) is defined by the RF input signal (fRFin) which

also defines the operating frequency of the local oscillator

(fLO). The basic clock cycle is TClk = 14/ fXTO giving

TClk = 2.066 ms for fRF = 868.3 MHz and

TClk = 1.961 ms for fRF = 915 MHz

TClk controls the following application-relevant parame-

ters:

D Timing of the polling circuit including bit check

D Timing of the analog and digital signal processing

D Timing of the register programming

D Frequency of the reset marker

D IF filter center frequency (fIF0)

Most applications are dominated by two transmission fre-

quencies: fTransmit = 915 MHz is mainly used in USA,

fTransmit = 868.3 MHz in Europe. In order to ease the

usage of all TClk-dependent parameters on this electrical

characteristics display three conditions for each parame-

ter.

D Application USA

(fXTO = 7.14063 MHz, TClk = 1.961 µs)

D Application Europe

(fXTO = 6.77617 MHz, TClk = 2.066 µs)

D Other applications

The electrical characteristic is given as a function of

TClk.

The clock cycle of some function blocks depends on the

selected baud-rate range (BR_Range) which is defined in

the OPMODE register. This clock cycle TXClk is defined

by the following formulas for further reference:

BR_Range = BR_Range0: TXClk = 8 × TClk

BR_Range1: TXClk = 4 × TClk

BR_Range2: TXClk = 2 × TClk

BR_Range3: TXClk = 1 × TClk

Polling Mode

According to figure 11, the receiver stays in polling mode

in a continuous cycle of three different modes. In sleep

mode the signal processing circuitry is disabled for the

time period TSleep while consuming low current of

IS = ISoff. During the start-up period, TStartup, all signal

processing circuits are enabled and settled. In the follow-

6 (32)

Rev. A2, 19-Oct-00

Preliminary Information

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