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C2320 데이터 시트보기 (PDF) - Supertex Inc

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C2320 Datasheet PDF : 4 Pages
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TC2320
N- and P-Channel Enhancement-Mode Dual MOSFET
Features
Low threshold
Low on resistance
Low input capacitance
Fast switching speeds
Freedom from secondary breakdown
Low input and output leakage
Independent, electrically isolated N- and P-
channels
Applications
Medical ultrasound transmitters
High voltage pulsers
Amplifiers
Buffers
Piezoelectric transducer drivers
General purpose line drivers
Logic level interface
General Description
The Supertex TC2320TG consists of a high voltage, low
threshold N- and P-channel MOSFET in an SO-8 package.
These low threshold enhancement-mode (normally-off)
transistors utilize an advanced vertical DMOS structure
and Supertex’s well-proven silicon-gate manufacturing
process. This combination produces devices with the
power handling capabilities of bipolar transistors and
with the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of
all MOS structures, these devices are free from thermal
runaway and thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications where
very low threshold voltage, high breakdown voltage, high
input impedance, low input capacitance, and fast switching
speeds are desired.
Ordering Information
Device
Package Options
8-Lead SOIC (Narrow Body)
TC2320
TC2320TG-G
-G indicates package is RoHS compliant (‘Green’)
BVDSS/BVDGS
(V)
N-Channel P-Channel
200
-200
RDS(ON)
(max)
(Ω)
N-Channel P-Channel
7.0
12
Pin Configuration
Absolute Maximum Ratings
Parameter
Value
Drain to source voltage
Drain to gate voltage
Gate to source voltage
BVDSS
BV
DGS
±20V
Operating and storage temperature -55°C to +150°C
Soldering temperature*
+300°C
Absolute Maximum Ratings are those values beyond which damage to the device
may occur. Functional operation under these conditions is not implied. Continuous
operation of the device at the absolute rating level may affect device reliability. All
voltages are referenced to device ground.
* Distance of 1.6mm from case for 10 seconds.
DRAIN_P
DRAIN_P
DRAIN_N
DRAIN_N
GATE_P
SOURCE_P
GATE_N
SOURCE_N
8-Lead SOIC (TG)
Product Marking
YYWW
C2320
LLLL
YY = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
8-Lead SOIC (TG)

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