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TC9028AF 데이터 시트보기 (PDF) - Toshiba

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TC9028AF Datasheet PDF : 21 Pages
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TC9028AP/AF
Table 2.1 Program counter values depending on conditions
Instruction or
operation
Condition
LD MBR,
#k
+
BSS a
SF = 1 (when branch
condition is satisfied)
SF = 0 (when branch
condition is not satisfied)
Program Counter (PC)
Page Assignment
Address Specification within Page
PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Memory bank register
contents
Value directly specified by BSS
instruction
+2
Instruction
execution
BSS a
Lower 6 bits of address
111111
SF = 1
Lower 6 bits of address
= 111111
SF=0
No change
+1
Value directly specified by instruction
Value directly specified by instruction
+1
CALLS a
0
0
0
0
0
Value directly specified
by instruction
0
RET
Value restored from stack
Instructions
other above
+1
Reset
0
0
0
0
0
0
0
0
0
0
2.2 Memory bank register (MBR)
The memory bank register is a 4bit write-only register. It holds the page specification (upper 4 bits of
the program counter) when a branch is made anywhere in program memory.
2.3 Stack register (STACK)
The stack is a 10bit register. When the [CALLS a] instruction is executed, the stack register saves the
contents of the program counter (return address) before the program jumps to the processing routine.
Only one level of subroutines can be used. When there are two calls, the first return address is
overwritten when the second return address is saved to the stack register.
When the program returns from the processing routine, execution of the [RET] instruction restores the
contents of the stack register to the program counter.
2.4 Data counter (DC)
When fixed data stored in the data table in program memory (ROM) are read, the data counter (DC)
are used to specify 4 bits of the address.
In addition to transferring data to the accumulator, the data counter is also equipped with increment
and decrement functions and can therefore be used as a general-purpose register.
Fixed data stored in the data table can be read using the table look-up instruction.
When the table look-up instruction is executed, the upper 6 bits of the ROM address are “101111” and
the lower 4 bits are the contents of the data counter (DC). These bits specify the last 16 bytes
(addresses 2F0~2FFH) of program memory for fixed data.
4
2002-04-19

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