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TDA4857 데이터 시트보기 (PDF) - Philips Electronics

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TDA4857 Datasheet PDF : 56 Pages
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Philips Semiconductors
I2C-bus autosync deflection controller for
PC monitors
Product specification
TDA4857PS
Frequency-locked loop
The frequency-locked loop can lock the horizontal
oscillator over a wide frequency range. This is achieved by
a combined search and PLL operation. The frequency
range is preset by two external resistors and the
recommended maximum ratio is -ff-m-m---a-i-n-x = 6---1-.--5-
This can, for instance, be a range from 15.625 to 90 kHz
with all tolerances included.
Without a horizontal sync signal the oscillator will be
free-running at fmin. Any change of sync conditions is
detected by the internal coincidence detector. A deviation
of more than 4% between horizontal sync and oscillator
frequency will switch the horizontal section into search
mode. This means that PLL1 control currents are switched
off immediately.
The internal frequency detector then starts tuning the
oscillator. Very small DC currents at HPLL1 (pin 26) are
used to perform this tuning with a well defined change rate.
When coincidence between horizontal sync and oscillator
frequency is detected, the search mode is first replaced by
a soft-lock mode which lasts for the first part of the next
vertical period. The soft-lock mode is then replaced by a
normal PLL operation. This operation ensures smooth
tuning and avoids fast changes of horizontal frequency
during catching.
In this concept it is not allowed to load HPLL1.
The frequency dependent voltage at this pin is fed
internally to HBUF (pin 27) via a sample-and-hold and
buffer stage. The sample-and-hold stage removes all
disturbances caused by horizontal sync or composite
vertical sync from the buffered voltage. An external
resistor connected between pins HBUF and HREF defines
the frequency range.
Out-of-lock indication (pin HUNLOCK)
Pin HUNLOCK is floating during search mode if no sync
pulses are applied, or if a protection condition is true.
All this can be detected by the microcontroller if a pull-up
resistor is connected to its own supply voltage.
For an additional fast vertical blanking at grid 1 of the
picture tube a 1 V signal referenced to ground is available
at this output. The continuous protection blanking
(see Section “Video clamping/vertical blanking generator”)
is also available at this pin. Horizontal unlock blanking can
be switched off, by control bit BLKDIS via the I2C-bus,
while vertical blanking is maintained.
Horizontal oscillator
The horizontal oscillator is of the relaxation type and
requires a capacitor of 10 nF to be connected at HCAP
(pin 29). For optimum jitter performance the value of 10 nF
must not be changed.
The minimum oscillator frequency is determined by a
resistor connected between pin HREF and ground.
A resistor connected between pins HREF and HBUF
defines the frequency range.
The reference current at pin HREF also defines the
integration time constant of the vertical sync integration.
Calculation of line frequency range
The oscillator frequencies fmin and fmax must first be
calculated. This is achieved by adding the spread of the
relevant components to the highest and lowest sync
frequencies fsync(min) and fsync(max). The oscillator is driven
by the currents in RHREF and RHBUF.
The following example is a 31.45 to 90 kHz application:
Table 1 Calculation of total spread
spread of
IC
CHCAP
RHREF, RHBUF
Total
for fmax
±3%
±2%
±2%
±7%
for fmin
±5%
±2%
±2%
±9%
Thus the typical frequency range of the oscillator in this
example is:
fmax = fsync(max) × 1.07 = 96.3 kHz
fmin = -f-s---y-1--n--.c-0--(--9m----i-n--) = 28.9 kHz
The TV mode is centred around fmin with a control range of
±10%. Activation of the TV mode is only allowed between
15.625 and 35 kHz.
The resistors RHREF and RHBUFpar can be calculated using
the following formulae:
RHREF = -f-m----i-n----+---7--0--8-.--0-×--0---k-1---H2-----z×----×-f--m2--k--i-n--[---k---H-----z----] = 2.61 k
RHBUFpar = -f-m----a---x---+---7--0--8--.-0--×--0--k-1---H2-----z×----×-f--m2--k--a--x---[--k----H-----z---]- = 726
2000 Jan 31
7

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