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TDAT162G52-3BAL

MARS®2G5 P-Pro (TDAT162G52) SONET/SDH 155/622/2488 Mbits/s Data Interface

Agere -> LSI Corporation 

Data Sheet

August 18, 2004

MARS2G5 P-Pro (TDAT162G52) SONET/SDH

155/622/2488 Mbits/s Data Interface

List of Tables (continued)

Table

Page

Table 52. TOAC Channel Input Versus Time-Slot Assignments .......................................................................... 198

Table 53. TTOAC OC-3 Signal Definition............................................................................................................. 198

Table 54. TTOAC OC-12 Signal Definition........................................................................................................... 199

Table 55. TTOAC OC-48 Signal Definition........................................................................................................... 200

Table 56. TTOAC Control Bits.............................................................................................................................. 201

Table 57. Rx/Tx TOHP-48 Interface Rates........................................................................................................... 204

Table 58. Transmit TOAC Interface Timing Specifications................................................................................... 206

Table 59. Receive TOAC Interface Timing Specifications.................................................................................... 207

Table 60. TOHP_MODE_VERR, Mode (R/W) and Block Version (RO)............................................................... 208

Table 61. TOHP_CH_INT, Channel Interrupt (R/W, RO) ..................................................................................... 208

Table 62. TOHP_DLT_EVT[A—D][1—2], 0x0802—0x0809, Delta/Event Registers (COR/COW-RO) ................ 209

Table 63. TOHP_RX_TX_STATE[A—D], 0x080A—0x080D, Receive/Transmit State Registers (RO) ............... 211

Table 64. TOHP_MSK[A—D][1—2], 0x080E—0x0815, Mask Bit Registers (R/W).............................................. 212

Table 65. TOHP_TRG[A—D], 0x0816—0x0819, Trigger Register 0 Æ 1 (R/W) ................................................. 213

Table 66. TOHP_CNTD[A—D][1—2], 0x081A—0x0821, Continuous N-Times Detect (CNTD) Values (R/W) .... 214

Table 67. TOHP_RCTL[A—D][1—2], 0x0822—0x0829, Receive Control [1—2] (R/W) ...................................... 215

Table 68. TOHP_RCTL[A—D][3], 0x082A—0x082D, Receive Control 3 (R/W) .................................................. 218

Table 69. TOHP_TCTL[A—D][1—2], 0x082E—0x0835, Transmit Control [1—2] (R/W) ..................................... 219

Table 70. TOHP_TCTL[A—D][3], 0x0836—0x0839, Transmit Control 3 (R/W) ................................................... 223

Table 71. TOHP_SD_SETR[A—D][1—2], 0x083A—0x0841, Signal Degrade BER Algorithm Set Control

Registers [1—2] (R/W)....................................................................................................................................... 224

Table 72. TOHP_SD_SETR[A—D][3], 0x0842—0x0845, Signal Degrade BER Algorithm Set Control

Register [3] (R/W) .............................................................................................................................................. 224

Table 73. TOHP_SD_CLEARR[A—D][1—2], 0x0846—0x084D, Signal Degrade BER Algorithm Clear

Control Registers [1—2] (R/W) .......................................................................................................................... 225

Table 74. TOHP_SD_CLEARR[A—D][3], 0x084E—0x0851, Signal Degrade BER Algorithm Clear Control

Register [3] (R/W) .............................................................................................................................................. 225

Table 75. TOHP_SF_SETR[A—D][1—2], 0x0852—0x0859, Signal Fail Set BER Algorithm Control

Registers [1—2] (R/W)....................................................................................................................................... 226

Table 76. TOHP_SF_SETR[A—D][3], 0x085A—0x085D, Signal Fail BER Algorithm Set Control

Register [3] (R/W) .............................................................................................................................................. 226

Table 77. TOHP_SF_CLEARR[A—D][1—2], 0x085E—0x0865, Signal Fail BER Algorithm Clear

Control Registers [1—2] (R/W) .......................................................................................................................... 227

Table 78. TOHP_SF_CLEARR[A—D][3], 0x0866—0x0869, Signal Fail BER Algorithm Clear

Control Register [3] (R/W).................................................................................................................................. 227

Table 79. Ns, L, M, and B Values to Set the BER Indicator ................................................................................. 229

Table 80. Ns, L, M, and B Values to Clear the BER Indicator .............................................................................. 230

Table 81. TOHP_B1ECNTR[A—D], 0x086A—0x086D, B1 Error Count (RO) ..................................................... 231

Table 82. TOHP_B2ECNTR[A—D][1—2], 0x086E—0x0875, B2 Error Count (RO) ............................................ 231

Table 83. TOHP_M1ECNTR[A—D][1—2], 0x0876—0x087D, M1 Error Count (RO) ........................................... 231

Table 84. TOHP_TOH_INSR[A—D][1—2], 0x087E—0x0885, Transmit OH Insert Value (R/W)......................... 232

Table 85. TOHP_RMONR[A—D][1—3], 0x0886—0x0891, Receive Monitor Value (RO).................................... 232

Table 86. TOHP_RJ0DMONR[A—D][1—32], 0x0892—0x0911, Receive J0/Z0 Monitor Value Registers (RO) . 233

Table 87. TOHP_TJ0DINSR[A—D][1—32], 0x0912—0x09A9, Transmit J0/Z0 Insert Value Registers (R/W) .... 234

Table 88. TOHP_TZ0DINSR[A—D][1—6], 0x09AA—0x09C1, Transmit Z0 Insert Value Registers (R/W) ......... 235

Table 89. Z0 Byte Ordering STS-48 Mode for Z0-1—Z0-47 ................................................................................ 236

Table 90. Z0 Byte Ordering STS-12 Mode for Z0-1—Z0-11 ................................................................................ 236

Table 91. Z0 Byte Ordering STS-3 Mode for Z0-1—Z0-2 .................................................................................... 236

Table 92. TOHP_SCRATCHR, 0x09C2, TOHP-48 Scratch Register (R/W) ........................................................ 236

Table 93. TOHP-48 Register Map ........................................................................................................................ 237

Table 94. E1/F1 Path Status Definition ................................................................................................................ 249

Agere Systems Inc.

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