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EL2120CN

100 MHz Current Feedback Amplifier

Elantec -> Intersil 

EL2120C

100 MHz Current Feedback Amplifier

Applications Information

The EL2120C represents the third generation of

current-feedback amplifier design It is designed

to provide good high-frequency performance over

wide supply voltage load impedance gain tem-

perature and manufacturing lot variations It is

a well-behaved amplifier in spite of its 100 MHz

bandwidth but a few precautions should be tak-

en to obtain maximum performance

The power supply pins must be well bypassed

0 01 mF ceramic capacitors are adequate but lead

length should be kept below and a ground

plane is recommended Bypassing with 4 7 mF

tantalum capacitors can improve settling charac-

teristics and smaller capacitors in parallel will

not be needed The lead length of sockets general-

ly deteriorates the amplifier’s frequency response

by exaggerating peaking and increasing ringing

in response to transients Short sockets cause lit-

tle degradation

Load capacitance also increases ringing and

peaking Capacitance greater than 35 pF should

be isolated with a series resistor Capacitance at

the VINb terminal has a similar effect and

should be kept below 5 pF Often the inductance

of the leads of a load capacitance will be self-reso-

nant at frequencies from 40 MHz to 200 MHz

and can cause oscillations A resonant load can be

de-Q’ed with a small series or parallel resistor A

‘‘snubber’’ can sometimes be used to reduce reso-

nances This is a resistor and capacitor in series

connected from output to ground Values of 68X

and 33 pF are typical Increasing the feedback

resistor can also improve frequency flatness

The VINa pin can oscillate in the 200 MHz to

500 MHz realm if presented with a resonant or

inductive source impedance A series 27X to 68X

resistor right on the VINa pin will suppress such

oscillations without affecting frequency response

b3 dB bandwidth is inversely proportional to

the value of feedback resistor RF The EL2120C

will tolerate values as low as 180X for a maxi-

mum bandwidth of about 140 MHz but peaking

will increase and tolerance to stray capacitance

will reduce At gains greater than 5 b3 dB band-

width begins to reduce and a smaller RF can be

used to maximize frequency response

The greatest frequency response flatness (to

0 1 dB for instance) occurs with RF e 300X to

330X Even the moderate peaking caused by low-

er values of RF will cause the gain to peak out of

the 0 1 dB window and higher values of RF will

cause an overcompensated response where the

gain falls below the 0 1 dB level Parasitic capaci-

tances will generally degrade the frequency flat-

ness

The EL2120C should not output a continuous

current above 50 mA as stated in the ABSO-

LUTE MAXIMUM RATINGS table The out-

put current limit is set to 120 mA at a die temper-

ature of 25 C and reduces to 85 mA at a die tem-

perature of 150 C This large current is needed to

slew load capacitance and drive low impedance

loads with low distortion but cannot be support-

ed continuously Furthermore package dissipa-

tion capabilities cannot be met under short-cir-

cuit conditions Current limit should not occur

longer than a few seconds

The output disable function of the EL2120C is

optimized for video performance While in dis-

able mode the feedthrough of the circuit can be

modeled as a 0 2 pF capacitor from VINa to the

output No more than g5V can be placed be-

tween VINa and VINb in disable mode but this

is compatible with common video signal levels

In disabled state the output can withstand about

1000 V ms slew rate signals impressed on it with-

out the output transistors turning on

The Disable pin logic level is referred to Va

With g5V supplies a CMOS or TTL driver with

pull-up resistor will suffice g15V supplies re-

quire a a14 a11V drive span or a15 a10V

nominally Open-collector TTL with a tapped

pull-up resistor can provide these spans The im-

pedance of the divider should be 1k or less for

optimum enable disable speed

The EL2120C enables in 50 ns or less When VIN

e 0 only a small switching glitch occurs at the

output When VIN is some other value the out-

put overshoots by about 0 7V when settling

toward its new enabled value

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