IC61SP12832-100B 데이터 시트보기 (PDF) - Integrated Circuit Solution Inc

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IC61SP12832-100B

128K x 32, 128K x 36 SYNCHRONOUS PIPELINED STATIC RAM

Integrated Circuit Solution Inc 

IC61SP12832

IC61SP12836

READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)

Symbol Parameter

-166

-150

-133

-117

-5

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

fMAX Clock Frequency

— 166 — 150 — 133 — 117 — 100 MHz

tKC

Cycle Time

6—

6.7 —

7.5 —

8.5 —

10 —

ns

tKH

Clock High Time

2.4 —

2.6 —

2.8 —

3.4 —

4—

ns

tKL

Clock Low Time

2.4 —

2.6 —

2.8 —

3.4 —

4—

ns

tKQ

Clock Access Time

— 3.5

— 3.8

—4

—4

—5

ns

tKQX(1) Clock High to Output Invalid

1.5 —

1.5 —

1.5 —

1.5 —

2.5 —

ns

tKQLZ(1,2) Clock High to Output Low-Z

0—

0—

0—

0—

0—

ns

tKQHZ(1,2) Clock High to Output High-Z

1.5 6

1.5 6.7

1.5 7.5

1.5 8.5

1.5 10

ns

tOEQ Output Enable to Output Valid — 3.5

— 3.5

— 3.8

—4

—5

ns

tOEQX(1) Output Disable to Output Invalid 0

—

0—

0—

0—

0—

ns

tOELZ(1,2) Output Enable to Output Low-Z 0

—

0—

0—

0—

0—

ns

tOEHZ(1,2) Output Disable to Output High-Z 2 3.5

2 3.5

2 3.8

24

2

5

ns

tAS

Address Setup Time

1.5 —

1.5 —

1.5 —

1.5 —

1.5 —

ns

tSS

Address Status Setup Time

1.5 —

1.5 —

1.5 —

1.5 —

1.5 —

ns

tWS

Write Setup Time

1.5 —

1.5 —

1.5 —

1.5 —

1.5 —

ns

tCES Chip Enable Setup Time

1.5 —

1.5 —

1.5 —

1.5 —

1.5 —

ns

tAVS Address Advance Setup Time 1.5 —

1.5 —

1.5 —

1.5 —

1.5 —

ns

tAH

Address Hold Time

0.5 —

0.5 —

0.5 —

0.5 —

0.5 —

ns

tSH

Address Status Hold Time

0.5 —

0.5 —

0.5 —

0.5 —

0.5 —

ns

tWH Write Hold Time

0.5 —

0.5 —

0.5 —

0.5 —

0.5 —

ns

tCEH Chip Enable Hold Time

0.5 —

0.5 —

0.5 —

0.5 —

0.5 —

ns

tAVH Address Advance Hold Time

0.5 —

0.5 —

0.5 —

0.5 —

0.5 —

ns

Note:

1. Guaranteed but not 100% tested. This parameter is periodically sampled.

2. Tested with load in Figure 2.

10

Integrated Circuit Solution Inc.

SSR019-0A 09/17/2001

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