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EL2005

High Accuracy Fast Buffer

Elantec -> Intersil 

EL2005 EL2005C

High Accuracy Fast Buffer

Applications Information

Recommended Layout Precautions

RF video printed circuit board layout rules

should be followed when using the EL2005 since

it will provide power gain to frequencies over

100 MHz Ground planes are recommended and

power supplies should be decoupled at each de-

vice with low inductance capacitors In addition

ground plane shielding may be extended to the

metal case of the device since it is electrically iso-

lated from internal circuitry Alternatively the

case should be connected to the output to mini-

mize input capacitance

Offset Voltage Adjustment

The EL2005’s offset voltages have been actively

trimmed by laser to meet guaranteed specifica-

tions when the offset preset pin is shorted to the

offset adjust pin The pre-calibration allows the

devices to be used in most DC or AC applications

without individually offset nulling each device If

offset null is desirable it is simply obtained by

leaving the offset preset pin open and connecting

a trim pot of 200X between the offset adjust pin

and Vb as illustrated on page 4

Operation from Single or Asymmetrical

Power Supplies

This device type may be readily used in applica-

tions where symmetrical supplies are unavailable

or not desirable In this case an apparent output

offset occurs due to the device’s voltage gain of

less than unity This additional output offset er-

ror may be predicted by

(Va bVb)

DVOj(1bAV)

2

e0 005 (Va bVb)

where AV e No load voltage gain typically 0 99

Vae Positive supply voltage

Vbe Negative supply voltage

For example with Va e a5V and Vb e

b12V DVO would be b35 mV This may be ad-

justed to zero as described above

Short Circuit Protection

In order to optimize transient response and out-

put swing output current limit has been omitted

from the EL2005 Short circuit protection may be

added by inserting appropriate value resistors be-

tween Va and VCa pins and Vb and VCb pins

as shown on page 4

Resistor values may be predicted by

Va Vb

RLIM j ISC e ISC

where ISC s 100 mA for EL2005

The inclusion of limiting resistors in the collec-

tors of the output transistors reduces output volt-

age swing Decoupling VCa and VCb pins with

capacitors to ground will retain full output swing

for transient pulses An alternate active current

limit technique that retains full DC output swing

is also shown on page 4 In this circuit the cur-

rent sources are saturated during normal opera-

tion thus applying full supply voltage to the VC

pins Under fault conditions the voltage decreas-

es as required by the overload

RLIM

j

VBE

ISC

e

0

60

6V

mA

e

10X

Capacitive Loading

The EL2005 is designed to drive capacitive loads

such as coaxial cables in excess of several thou-

sand picofarads without susceptibility to oscilla-

tion However peak current resulting from

(C c dV dt) should be limited below absolute

maximum peak current ratings for the devices

Thus

DVIN

Dt

c

CL

s

IOUT

s

g250

mA

In addition power dissipation resulting from

driving capacitive loads plus standby power

should be kept below the total package power

rating

PDpkg t PDC a PAC

PDpkg t (Va b Vb) c IS a PAC

PAC j (VP-P)2 c f c CL

where VP-P e Peak-to-peak output voltage

swing

f e Frequency

CL e Load Capacitance

7

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